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STANDARD PRODUCT DATA SHEET PMC-1970624 ISSUE 10
PM4351 COMET
COMBINED E1/T1 TRANSCEIVER
PM4351
COMET
COMBINED E1/T1 TRANSCEIVER/FRAMER
DATA SHEET
ISSUE10: NOVEMBER 2000
PMC-Sierra, Inc.
105 - 8555 Baxter Place Burnaby, BC Canada V5A 4V7 604 .415.6000
STANDARD PRODUCT DATA SHEET PMC-1970624 ISSUE 10
PM4351 COMET
COMBINED E1/T1 TRANSCEIVER
PMC-Sierra, Inc.
105 - 8555 Baxter Place Burnaby, BC Canada V5A 4V7 604 .415.6000
STANDARD PRODUCT DATA SHEET PMC-1970624 ISSUE 10
PM4351 COMET
COMBINED E1/T1 TRANSCEIVER
CONTENTS 1 FEATURES .............................................................................................. 1 1.1 1.2 2 3 4 5 6 7 8 9 Receiver section:........................................................................... 2 Transmitter section: ....................................................................... 4
APPLICATIONS ....................................................................................... 6 REFERENCES......................................................................................... 7 APPLICATION EXAMPLE.......................................................................11 BLOCK DIAGRAM ................................................................................. 13 DESCRIPTION ...................................................................................... 14 PIN DIAGRAMs...................................................................................... 17 PIN DESCRIPTION................................................................................ 19 FUNCTIONAL DESCRIPTION............................................................... 32 9.1 9.2 9.3 9.4 9.5 9.6 9.7 9.8 9.9 9.10 9.11 Receive Interface ........................................................................ 32 Clock and Data Recovery (CDRC) .............................................. 35 T1 Framer ................................................................................... 38 E1 Framer ................................................................................... 39 T1 Inband Loopback Code Detector (IBCD) ............................... 47 T1 Pulse Density Violation Detector (PDVD)............................... 47 Performance Monitor Counters (PMON) ..................................... 47 T1 Bit Oriented Code Detector (RBOC) ...................................... 48 HDLC Receiver (RDLC) .............................................................. 48 T1 Alarm Integrator (ALMI).......................................................... 49 Receive Elastic Store (RX-ELST) ................................................ 50
PROPRIETARY AND CONFIDENTIAL
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STANDARD PRODUCT DATA SHEET PMC-1970624 ISSUE 10
PM4351 COMET
COMBINED E1/T1 TRANSCEIVER
9.12 9.13 9.14 9.15 9.16 9.17 9.18 9.19 9.20 9.21 9.22 9.23 9.24 9.25 9.26 9.27 9.28 9.29 9.30 9.31 9.32 10
Receive Jitter Attenuator (RJAT) ................................................. 51 Signaling Extractor (SIGX) .......................................................... 51 Receive Per-channel Serial Controller (RPSC) ........................... 52 T1 Signaling Aligner (SIGA)......................................................... 52 T1 Basic Transmitter (XBAS) ...................................................... 52 E1 Transmitter (E1-TRAN) .......................................................... 53 Transmit Elastic Store (TX-ELST) ............................................... 53 Transmit Per-Channel Serial Controller (TPSC).......................... 54 T1 Inband Loopback Code Generator (XIBC) ............................. 54 T1 Bit Oriented Code Generator (XBOC) .................................... 55 HDLC Transmitters...................................................................... 55 T1 Automatic Performance Report Generation ........................... 56 Pulse Density Enforcer (XPDE)................................................... 57 Pseudo Random Pattern Generation and Detection ................... 57 Transmit Jitter Attenuator (TJAT)................................................. 57 Timing Options (TOPS) ............................................................... 62 Line Transmitter........................................................................... 62 Backplane Receive Interface (BRIF) ........................................... 63 Backplane Transmit Interface (BTIF)........................................... 64 JTAG Test Access Port ................................................................ 65 Microprocessor Interface (MPIF) ................................................. 65
REGISTER DESCRIPTION ................................................................... 66 10.1 Normal Mode Register Memory Map........................................... 66
11
NORMAL MODE REGISTER DESCRIPTION ....................................... 75
PROPRIETARY AND CONFIDENTIAL
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STANDARD PRODUCT DATA SHEET PMC-1970624 ISSUE 10
PM4351 COMET
COMBINED E1/T1 TRANSCEIVER
12
TEST FEATURES DESCRIPTION ...................................................... 349 12.1 12.2 Test Mode 0............................................................................... 351 JTAG Test Port .......................................................................... 353
13
FUNCTIONAL TIMING......................................................................... 356 13.1 13.2 Transmit Backplane Interface.................................................... 356 Receive Backplane Interface..................................................... 362
14
OPERATION ........................................................................................ 367 14.1 14.2 Configuring the COMET from Reset.......................................... 367 Using the Internal HDLC Transmitters....................................... 373 14.2.1 Automatic transmission mode using interrupts: .............. 374 14.2.2 TDPR Interrupt Routine: ................................................. 375 14.2.3 Automatic transmission mode using polling:................... 376 14.3 14.4 14.5 14.6 Using the Internal HDLC Receivers........................................... 377 T1 Automatic Performance Report Format................................ 379 Using the Transmit Line Pulse Generator ................................. 381 Using the Line Receiver ............................................................ 401 14.6.1 T1 Performance Monitor Mode........................................411 14.7 Using the Test Pattern Generator.............................................. 414 14.7.1 Common Test Patterns ................................................... 415 14.8 Using the Loopback Modes....................................................... 417 14.8.1 Line Loopback ................................................................ 417 14.8.2 Payload Loopback .......................................................... 418 14.8.3 Diagnostic Digital Loopback ........................................... 419 14.8.4 Per-Channel Loopback................................................... 420
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STANDARD PRODUCT DATA SHEET PMC-1970624 ISSUE 10
PM4351 COMET
COMBINED E1/T1 TRANSCEIVER
14.9
Using the Per-Channel Serial Controllers.................................. 421 14.9.1 Initialization..................................................................... 421 14.9.2 Direct Access Mode ........................................................ 421 14.9.3 Indirect Access Mode ..................................................... 421
14.10 Isolating an Interrupt.................................................................. 422 14.11 Using the Performance Monitor Counter Values ....................... 422 14.12 JTAG Support............................................................................ 428 15 16 17 ABSOLUTE MAXIMUM RATINGS ....................................................... 438 D.C. CHARACTERISTICS ................................................................... 439 A.C. TIMING CHARACTERISTICS...................................................... 442 17.1 17.2 17.3 17.4 17.5 17.6 18 19 Microprocessor Interface Timing Characteristics....................... 442 Transmit Backplane Interface (Figure 71, Figure 73) ................ 446 Receive Backplane Interface (Figure 75, Figure 77) ................. 448 Receive Digital Interface (Figure 79) ......................................... 452 Transmit Digital Interface (Figure 81) ........................................ 453 JTAG Port Interface (Figure 83) ................................................ 455
ORDERING AND THERMAL INFORMATION...................................... 458 MECHANICAL INFORMATION............................................................ 459
PROPRIETARY AND CONFIDENTIAL
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STANDARD PRODUCT DATA SHEET PMC-1970624 ISSUE 10
PM4351 COMET
COMBINED E1/T1 TRANSCEIVER
LIST OF REGISTERS Register 000H: Global Configuration ................................................................ 76 Register 001H: Clock Monitor ........................................................................... 78 Register 002H: Receive Options....................................................................... 80 Register 003H: Receive Line Interface Configuration....................................... 82 Register 004H: Transmit Line Interface Configuration ...................................... 85 Register 005H: Transmit Framing and Bypass Options .................................... 87 Register 006H: Transmit Timing Options .......................................................... 90 Register 007H: Interrupt Source #1 .................................................................. 95 Register 008H: Interrupt Source #2 .................................................................. 96 Register 009H: Interrupt Source #3 .................................................................. 97 Register 00AH: Master Diagnostics .................................................................. 98 Register 00BH: Master Test ............................................................................ 100 Register 00CH: Analog Diagnostics................................................................ 102 Register 00DH: Revision/Chip ID/Global PMON Update ................................ 103 Register 00EH: Reset ..................................................................................... 104 Register 00FH: PRGD Positioning/Control and HDLC Control ....................... 105 Register 010H: CDRC Configuration .............................................................. 108 Register 011H: CDRC Interrupt Control...........................................................110 Register 012H: CDRC Interrupt Status ............................................................ 111 Register 013H: Alternate Loss of Signal Status ...............................................113 Register 014H: RJAT Interrupt Status..............................................................114 Register 015H: RJAT Divider N1 Control .........................................................115
PROPRIETARY AND CONFIDENTIAL
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STANDARD PRODUCT DATA SHEET PMC-1970624 ISSUE 10
PM4351 COMET
COMBINED E1/T1 TRANSCEIVER
Register 016H: RJAT Divider N2 Control .........................................................116 Register 017H: RJAT Configuration.................................................................117 Register 018H: TJAT Interrupt Status ..............................................................119 Register 019H: TJAT Jitter Attenuator Divider N1 Control .............................. 120 Register 01AH: TJAT Divider N2 Control ........................................................ 121 Register 01BH: TJAT Configuration ................................................................ 123 Register 01CH: RX-ELST Configuration ......................................................... 125 Register 01DH: RX-ELST Interrupt Enable/Status.......................................... 126 Register 01EH: RX-ELST Idle Code ............................................................... 127 Register 020H: TX-ELST Configuration .......................................................... 128 Register 021H: TX-ELST Interrupt Enable/Status........................................... 129 Register 028H: RXCE Receive Data Link 1 Control ....................................... 130 Register 029H: RXCE Receive Data Link 1 Bit Select.................................... 132 Register 02AH: RXCE Receive Data Link 2 Control ....................................... 133 Register 02BH: RXCE Receive Data Link 2 Bit Select ................................... 134 Register 02CH: RXCE Receive Data Link 3 Control....................................... 135 Register 02DH: RXCE Receive Data Link 3 Bit Select ................................... 136 Register 030H: BRIF Configuration ................................................................ 137 Register 031H: BRIF Frame Pulse Configuration ........................................... 140 Register 032H: BRIF Parity/F-bit Configuration .............................................. 144 Register 033H: BRIF Time Slot Offset ............................................................ 146 Register 034H: BRIF Bit Offset ....................................................................... 147 Register 038H: TXCI Transmit Data Link 1 Control ........................................ 149 Register 039H: TXCI Transmit Data Link 1 Bit Select..................................... 151
PROPRIETARY AND CONFIDENTIAL
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STANDARD PRODUCT DATA SHEET PMC-1970624 ISSUE 10
PM4351 COMET
COMBINED E1/T1 TRANSCEIVER
Register 03AH: TXCI Transmit Data Link 2 Control ........................................ 152 Register 03BH: TXCI Transmit Data Link 2 Bit Select .................................... 153 Register 03CH: TXCI Transmit Data Link 3 Control........................................ 154 Register 03DH: TXCI Transmit Data Link 3 Bit Select .................................... 155 Register 040H: BTIF Configuration................................................................. 156 Register 041H: BTIF Frame Pulse Configuration ........................................... 159 Register 042H: BTIF Parity Configuration and Status..................................... 161 Register 043H: BTIF Time Slot Offset ............................................................ 163 Register 044H: BTIF Bit Offset ....................................................................... 164 Register 048H: T1 FRMR Configuration ......................................................... 166 Register 049H: T1 FRMR Interrupt Enable..................................................... 168 Register 04AH: T1 FRMR Interrupt Status...................................................... 170 Register 04CH: IBCD Configuration ............................................................... 172 Register 04DH: IBCD Interrupt Enable/Status ................................................ 173 Register 04EH: IBCD Activate Code............................................................... 175 Register 04FH: IBCD Deactivate Code........................................................... 176 Register 050H: SIGX Configuration Register (COSS = 0) ............................. 177 Register 050H: SIGX Change of Signaling State Register (COSS = 1) .......... 179 Register 051H: SIGX Timeslot Indirect Status (COSS = 0)............................ 180 Register 051H: SIGX Change Of Signaling State Change (COSS=1) ............ 181 Register 052H: SIGX Timeslot Indirect Address/Control (COSS = 0) ............. 182 Register 052H: SIGX Change of Signaling State Register (COSS = 1) .......... 183 Register 053H: SIGX Timeslot Indirect Data Buffer (COSS = 0) .................... 184 Register 053H: SIGX Change of Signaling State (COSS = 1) ........................ 185
PROPRIETARY AND CONFIDENTIAL
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STANDARD PRODUCT DATA SHEET PMC-1970624 ISSUE 10
PM4351 COMET
COMBINED E1/T1 TRANSCEIVER
Register 054H: T1 XBAS Configuration.......................................................... 191 Register 055H: T1 XBAS Alarm Transmit ....................................................... 193 Register 056H: T1 XIBC Control..................................................................... 194 Register 057H: T1 XIBC Loopback Code ....................................................... 196 Register 058H: PMON Interrupt Enable/Status............................................... 197 Register 059H: PMON Framing Bit Error Count ............................................. 199 Register 05AH: PMON OOF/COFA/Far End Block Error Count LSB ............. 200 Register 05BH: PMON OOF/COFA/Far End Block Error Count MSB ............ 201 Register 05CH: PMON Bit Error/CRC Error Count LSB ................................. 202 Register 05DH: PMON Bit Error/CRC Error Count MSB ................................ 203 Register 05EH: PMON LCV Count (LSB) ....................................................... 204 Register 05FH: PMON LCV Count (MSB) ...................................................... 205 Register 060H: T1 ALMI Configuration ........................................................... 206 Register 061H: T1 ALMI Interrupt Enable ....................................................... 208 Register 062H: T1 ALMI Interrupt Status ........................................................ 209 Register 063H: T1 ALMI Alarm Detection Status ............................................ 210 Register 065H: T1 PDVD Interrupt Enable/Status .......................................... 212 Register 067H: T1 XBOC Code ...................................................................... 214 Register 069H: T1 XPDE Interrupt Enable/Status .......................................... 215 Register 06AH: T1 RBOC Enable................................................................... 217 Register 06BH: T1 RBOC Code Status .......................................................... 218 Register 06CH: TPSC Configuration .............................................................. 219 Register 06DH: TPSC P Access Status ........................................................ 220 Register 06EH: TPSC Channel Indirect Address/Control ............................... 221
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STANDARD PRODUCT DATA SHEET PMC-1970624 ISSUE 10
PM4351 COMET
COMBINED E1/T1 TRANSCEIVER
Register 06FH: TPSC Channel Indirect Data Buffer ....................................... 222 Register 070H: RPSC Configuration............................................................... 231 Register 071H: RPSC P Access Status ........................................................ 232 Register 072H: RPSC Channel Indirect Address/Control ............................... 233 Register 073H: RPSC Channel Indirect Data Buffer....................................... 234 Register 078H: T1 APRM Configuration/Control............................................. 239 Register 079H: T1 APRM Manual Load.......................................................... 241 Register 07AH: T1 APRM Interrupt Status...................................................... 242 Register 07BH: T1 APRM One Second Content Octet 2 ................................ 243 Register 07CH: T1 APRM One Second Content Octet 3 ................................ 244 Register 07DH: T1 APRM One Second Content Octet 4 ................................ 245 Register 07EH: T1 APRM One Second Content MSB (Octet 5) ..................... 246 Register 07FH: T1 APRM One Second Content LSB (Octet 6) ..................... 248 Register 080H: E1 TRAN Configuration ......................................................... 250 Register 081H: E1 TRAN Transmit Alarm/Diagnostic Control......................... 253 Register 082H: E1 TRAN International/National Control ................................ 255 Register 083H: E1 TRAN Extra Bits Control ................................................... 256 Register 084H: E1 TRAN Interrupt Enable ..................................................... 257 Register 085H: E1 TRAN Interrupt Status ...................................................... 259 Register 086H: E1 TRAN National Bits Codeword Select .............................. 261 Register 087H: E1 TRAN National Bits Codeword ......................................... 263 Register 090H: E1 FRMR Frame Alignment Options...................................... 265 Register 091H: E1 FRMR Maintenance Mode Options .................................. 267 Register 092H: E1 FRMR Framing Status Interrupt Enable............................ 269
PROPRIETARY AND CONFIDENTIAL
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STANDARD PRODUCT DATA SHEET PMC-1970624 ISSUE 10
PM4351 COMET
COMBINED E1/T1 TRANSCEIVER
Register 093H: E1 FRMR Maintenance/Alarm Status Interrupt Enable.......... 270 Register 094H: E1 FRMR Framing Status Interrupt Indication ....................... 271 Register 095H: E1 FRMR Maintenance/Alarm Status Interrupt Indication...... 272 Register 096H: E1 FRMR Framing Status ...................................................... 273 Register 097H: E1 FRMR Maintenance/Alarm Status .................................... 275 Register 098H: E1 FRMR Timeslot 0 International/National Bits .................... 277 Register 099H: E1 FRMR CRC Error Counter - LSB...................................... 279 Register 09AH: E1 FRMR CRC Error Counter - MSB/Timeslot 16 Extra Bits 280 Register 09BH: E1 FRMR National Bit Codeword Interrupt Enables.............. 283 Register 09CH: E1 FRMR National Bit Codeword Interrupts.......................... 285 Register 09DH: E1 FRMR National Bit Codeword .......................................... 286 Register 09EH: E1 FRMR Frame Pulse/Alarm/V5.2 Link ID Interrupt Enables287 Register 09FH: E1 FRMR Frame Pulse/Alarm Interrupts ............................... 289 Register 0A8H (#1), 0B0H (#2), 0B8H (#3): TDPR Configuration .................. 291 Register 0A9H (#1), 0B1H (#2), 0B9H (#3): TDPR Upper Transmit Threshold293 Register 0AAH (#1), 0B2H (#2), 0BAH (#3): TDPR Lower Interrupt Threshold294 Register 0ABH (#1), 0B3H (#2), 0BBH (#3): TDPR Interrupt Enable ............. 295 Register 0ACH (#1), 0B4H (#2), 0BCH (#3): TDPR Interrupt Status .............. 296 Register 0ADH (#1), 0B5H (#2), 0BDH (#3): TDPR Transmit Data ................ 298 Registers 0C0H (#1), 0C8H (#2), 0D0H (#3): RDLC Configuration ................ 299 Registers 0C1H (#1), 0C9H (#2), 0D1H (#3): RDLC Interrupt Control ........... 301 Registers 0C2H (#1), 0CAH (#2), 0D2H (#3): RDLC Status ........................... 302 Registers 0C3H (#1), 0CBH (#2), 0D3H (#3): RDLC Data ............................. 305 Registers 0C4H (#1), 0CCH (#2), 0D4H (#3): RDLC Primary Address Match 306
PROPRIETARY AND CONFIDENTIAL
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STANDARD PRODUCT DATA SHEET PMC-1970624 ISSUE 10
PM4351 COMET
COMBINED E1/T1 TRANSCEIVER
Registers 0C5H (#1), 0CDH (#2), 0D5H (#3): RDLC Secondary Address Match ............................................................................................................. 307 Register 0D6H: CSU Configuration ................................................................ 308 Register 0D8H: RLPS Equalization Indirect Data ........................................... 310 Register 0D9H: RLPS Equalization Indirect Data ............................................311 Register 0DAH: RLPS Equalization Indirect Data........................................... 312 Register 0DBH: RLPS Equalization Indirect Data........................................... 313 Register 0DCH: RLPS Equalizer Voltage Reference ...................................... 314 Register 0E0H: PRGD Control........................................................................ 315 Register 0E1H: PRGD Interrupt Enable/Status............................................... 317 Register 0E2H: PRGD Shift Register Length.................................................. 319 Register 0E3H: PRGD Tap ............................................................................. 320 Register 0E4H: PRGD Error Insertion ............................................................ 321 Register 0E8H: PRGD Pattern Insertion #1.................................................... 322 Register 0E9H: PRGD Pattern Insertion #2.................................................... 323 Register 0EAH: PRGD Pattern Insertion #3 ................................................... 324 Register 0EBH: PRGD Pattern Insertion #4 ................................................... 325 Register 0ECH: PRGD Pattern Detector #1 ................................................... 326 Register 0EDH: PRGD Pattern Detector #2 ................................................... 327 Register 0EEH: PRGD Pattern Detector #3.................................................... 328 Register 0EFH: PRGD Pattern Detector #4.................................................... 329 Register 0F0H: XLPG Line Driver Configuration............................................. 330 Register 0F1H: XLPG Control/Status.............................................................. 332 Register 0F2H: XLPG Pulse Waveform Storage Write Address ..................... 333
PROPRIETARY AND CONFIDENTIAL
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STANDARD PRODUCT DATA SHEET PMC-1970624 ISSUE 10
PM4351 COMET
COMBINED E1/T1 TRANSCEIVER
Register 0F3H: XLPG Pulse Waveform Storage Data .................................... 334 Register 0F4H: XLPG Analog Test Negative Control ...................................... 335 Register 0F5H: XLPG Analog Test Positive Control........................................ 336 Register 0F6H: XLPG Fuse Data Select......................................................... 337 Register 0F8H: RLPS Configuration and Status ............................................. 338 Register 0F9H: RLPS ALOS Detection/Clearance Threshold......................... 340 Register 0FAH: RLPS ALOS Detection Period ............................................... 342 Register 0FBH: RLPS ALOS Clearance Period.............................................. 343 Register 0FCH: RLPS Equalization Indirect Address...................................... 344 Register 0FDH: RLPS Equalization Read/WriteB Select ................................ 345 Register 0FEH: RLPS Equalizer Loop Status and Control.............................. 346 Register 0FFH: RLPS Equalizer Configuration ............................................... 347 Register 00BH: COMET Master Test .............................................................. 350
PROPRIETARY AND CONFIDENTIAL
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STANDARD PRODUCT DATA SHEET PMC-1970624 ISSUE 10
PM4351 COMET
COMBINED E1/T1 TRANSCEIVER
LIST OF FIGURES Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure 8 Figure 9 Figure 10 Figure 11 Figure 12 - Wireless Base Station Application ................................................11 - V5.1 Interface Application ............................................................ 12 PM4351-RI COMET Pin Diagram .................................................. 17 PM4351-NI COMET Pin Diagram .................................................. 18 - External Analog Interface Circuits................................................ 33 - T1 Jitter Tolerance ....................................................................... 37 - Compliance with ITU-T Specification G.823 for E1 Input Jitter .... 38 - CRC Multiframe Alignment Algorithm........................................... 43 - TJAT Jitter Tolerance ................................................................... 59 - TJAT Minimum Jitter Tolerance vs. XCLK Accuracy .................... 60 - TJAT Jitter Transfer...................................................................... 61 - Transmit Timing Options .............................................................. 94
Figure 13 - Transmit Backplane: CMS=0, FE=1, DE=1, BTFP is Input........... 356 Figure 14 - Transmit Backplane: CMS=0, FE=1, DE=0, BTFP is Input........... 356 Figure 15 - Transmit Backplane: CMS=1, FE=1, DE=1, BTFP is Input........... 356 Figure 16 - Transmit Backplane: CMS=1, FE=0, DE=1, BTFP is Input.......... 356 Figure 17 - Transmit Backplane: CMS=0, FE=1, DE=1, BTFP is Output........ 357 Figure 18 - Transmit Backplane: CMS=0, FE=1, DE=0, BTFP is Output........ 357 Figure 19 Figure 20 Figure 21 Figure 22 - Transmit Backplane at 1.544 Mbit/s (T1 mode) ......................... 357 - Transmit Backplane at 2.048 Mbit/s (T1 mode) ......................... 358 - Transmit Backplane at 2.048 Mbit/s (E1 mode) ......................... 359 - Transmit Backplane at 4.096 Mbit/s (T1 mode) ......................... 359
PROPRIETARY AND CONFIDENTIAL
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STANDARD PRODUCT DATA SHEET PMC-1970624 ISSUE 10
PM4351 COMET
COMBINED E1/T1 TRANSCEIVER
Figure 23 Figure 24 Figure 25 Figure 26 Figure 27 Figure 28 Figure 29 Figure 30 Figure 31 Figure 32 Figure 33 Figure 34 Figure 35 Figure 36 Figure 37 Figure 38 Figure 39 Figure 40 Figure 41 Figure 42 Figure 43 Figure 44 Figure 45 Figure 46
- Transmit Backplane at 4.096 Mbit/s (E1 mode) ......................... 360 - Transmit Backplane at 8.192 Mbit/s (T1 mode) ......................... 360 - Transmit Backplane at 8.192 Mbit/s (E1 mode) ......................... 361 - Concentration Highway Interface Timing, Example 1 ................ 361 - Concentration Highway Interface Timing, Example 2 ................ 361 - Receive Backplane at 1.544 Mbit/s (T1 Mode) .......................... 362 - Receive Backplane at 2.048 Mbit/s (T1 Mode) .......................... 363 - Receive Backplane at 2.048 Mbit/s (E1 Mode).......................... 363 - Receive Backplane at 4.096 Mbit/s (T1 Mode) ......................... 364 - Receive Backplane at 4.096 Mbit/s (E1 Mode)......................... 364 - Receive Backplane at 8.192 Mbit/s (T1 Mode) ......................... 365 - Receive Backplane at 8.192 Mbit/s (E1 Mode)......................... 365 - Concentration Highway Interface Timing, Example 1 ............... 366 - Concentration Highway Interface Timing, Example 2 ............... 366 - Typical Data Frame.................................................................... 377 - Pattern Generator Structure....................................................... 414 - Line Loopback ........................................................................... 418 - Payload Loopback ..................................................................... 419 - Diagnostic Digital Loopback....................................................... 420 - LCV Count vs. BER (E1 mode).................................................. 424 - FER Count vs. BER (E1 mode) ................................................. 424 - CRCE Count vs. BER (E1 mode) .............................................. 425 - LCV Count vs. BER (T1 mode).................................................. 426 - FER Count vs. BER (T1 ESF mode).......................................... 426
PROPRIETARY AND CONFIDENTIAL
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STANDARD PRODUCT DATA SHEET PMC-1970624 ISSUE 10
PM4351 COMET
COMBINED E1/T1 TRANSCEIVER
Figure 47 Figure 48 Figure 49 Figure 50 Figure 51 Figure 52 Figure 53 Figure 54 Figure 55 Figure 56 Figure 57 Figure 58 Figure 59 Figure 60 Figure 61 Figure 62 Figure 63
- CRCE Count vs. BER (T1 ESF mode)....................................... 427 - CRCE Count vs. BER (T1 SF mode) ......................................... 427 - Boundary Scan Architecture ...................................................... 428 - TAP Controller Finite State Machine .......................................... 430 - Input Observation Cell (IN_CELL) ............................................. 435 - Output Cell (OUT_CELL) ........................................................... 436 - Bidirectional Cell (IO_CELL) ...................................................... 436 - Layout of Output Enable and Bidirectional Cells........................ 437 - Microprocessor Read Access Timing......................................... 443 - Microprocessor Write Access Timing ......................................... 445 - Backplane Transmit Input Timing Diagram ................................ 447 - Backplane Transmit Output Timing Diagram ............................. 448 - Backplane Receive Input Timing Diagram ................................. 450 - Backplane Receive Output Timing Diagram .............................. 451 - Digital Receive Interface Timing Diagram .................................. 453 - Digital Transmit Interface Timing Diagram ................................. 454 - JTAG Port Interface Timing........................................................ 456
PROPRIETARY AND CONFIDENTIAL
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STANDARD PRODUCT DATA SHEET PMC-1970624 ISSUE 10
PM4351 COMET
COMBINED E1/T1 TRANSCEIVER
LIST OF TABLES Table 1 Table 2 Table 3 Table 4 Table 5 Table 6 Table 7 Table 8 Table 9 Table 10 Table 11 Table 12 Table 13 Table 14 Table 15 Table 16 Table 17 Table 18 Table 19 Table 20 Table 21 Table 22 - Backplane Transmit Interface (4 pins) ......................................... 19 - Backplane Receive Interface (4 pins) .......................................... 21 - Transmit Line Interface (6 pins) ................................................... 23 - Receive Line Interface (4 pins) .................................................... 24 - Timing Options Control (5 pins) ................................................... 24 - Analog Support Circuitry (4 pins) ................................................. 25 - JTAG (IEEE 1149.1) Boundary Scan Test Interface (5 pins)........ 26 - Microprocessor Interface (23 pins) .............................................. 26 - Power and Ground (25 pins)........................................................ 28 - PM4351-RI Pin Summary ............................................................ 30 PM4351-NI Pin Summary .............................................................. 30 - External Component Descriptions ............................................... 34 - Typical Input Return Loss at Receiver ......................................... 35 - Termination Resistors, Transformer Ratios and TRL ................... 35 - E1-FRMR Framing States............................................................ 44 - Normal Mode Register Memory Map ........................................... 66 - TJAT FIFO Output Clock Source ................................................ 90 - TJAT PLL Source ......................................................................... 91 - Transmit Timing Options Summary.............................................. 91 - Loss of Signal Thresholds.......................................................... 109 - Receive Backplane NXDS0 Mode Selection ............................. 137 - Receive Backplane Rate............................................................ 139
PROPRIETARY AND CONFIDENTIAL
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STANDARD PRODUCT DATA SHEET PMC-1970624 ISSUE 10
PM4351 COMET
COMBINED E1/T1 TRANSCEIVER
Table 23 Table 24 Table 25 Table 26 Table 27 Table 28 Table 29 Table 30 Table 31 Table 32 Table 33
- E1 Receive Backplane Frame Pulse Configurations ................. 142 - Receive Backplane Tri-state Control.......................................... 145 - Receive Backplane Bit Offset for CMS = 0 ................................ 148 - Receive Backplane Bit Offset for CMS = 1 ................................ 148 - Transmit Backplane NXDS0 Mode Selection............................. 156 - Transmit Backplane Rate........................................................... 158 - Transmit Backplane Bit Offset for CMS = 0 ............................... 165 - Transmit Backplane Bit Offset for CMS = 1 ............................... 165 - T1 Framing Modes..................................................................... 167 - Loopback Code Configurations ................................................. 172 - SIGX Indirect Register Map ....................................................... 185
Table 34 - SIGX Indirect Registers 10H - 1FH: Current Timeslot/Channel Signaling Data ................................................................................................ 187 Table 35 - SIGX Indirect Registers 20H - 3FH: Delayed Timeslot/Channel Signaling Data ................................................................................................ 188 Table 36 Table 37 Table 38 Table 39 Table 40 Table 41 Table 42 Table 43 Table 44 Table 45 - Indirect Registers 40H - 5FH: Per-Timeslot Configuration ......... 188 - SIGX Per-Channel T1 Data Conditioning................................... 189 - SIGX Per-Channel E1 Data Conditioning .................................. 189 - T1 Framing Formats .................................................................. 192 - T1 Zero Code Suppression Formats.......................................... 192 - Transmit In-band Code Length .................................................. 194 - T1 Framing Modes..................................................................... 207 - TPSC Indirect Register Map ...................................................... 222 - TPSC Indirect Registers 20H-3FH: PCM Data Control byte ...... 224 - TPSC Transmit Data Conditioning ............................................. 225
PROPRIETARY AND CONFIDENTIAL
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STANDARD PRODUCT DATA SHEET PMC-1970624 ISSUE 10
PM4351 COMET
COMBINED E1/T1 TRANSCEIVER
Table 46 Table 47 Table 48 Table 49 Table 50 Table 51 Table 52 Table 53 Table 54 Table 55 Table 56 byte Table 57 byte Table 58 Table 59 Table 60 Table 61 Table 62 Table 63 Table 64 Table 65 Table 66 Table 67 Table 68
- Transmit Test Pattern Modes ..................................................... 225 - Transmit Zero Code Suppression Formats ................................ 226 - TPSC Indirect Registers 40H-5FH: IDLE Code byte.................. 227 - TPSC Indirect Registers 60H-7FH: Signaling/E1 Control byte... 227 - Transmit Per-timeslot Data Manipulation ................................... 228 - A-Law Digital Milliwatt Pattern.................................................... 228 - -Law Digital Milliwatt Pattern .................................................... 229 - RPSC Indirect Register Map...................................................... 234 - RPSC Indirect Registers 20H-3FH: PCM Data Control byte...... 236 - Receive Test Pattern Modes ...................................................... 236 - RPSC Indirect Registers 40H-5FH: Data Trunk Conditioning Code 238 - RPSC Indirect Registers 61H-7FH: Signaling Trunk Conditioning 238 - NmNi Settings............................................................................ 249 - E1 Signaling Insertion Mode ...................................................... 250 - E1 Timeslot 0 Bit 1 Insertion Control Summary ......................... 252 - National Bits Codeword Select .................................................. 262 - Timeslot 0 Bit Position Allocation ............................................... 278 - Signaling Multiframe Timeslot 16, Frame 0 Bit Positions ........... 282 - E1 FRMR Codeword Select....................................................... 284 - Receive Packet Byte Status....................................................... 302 - Clock Synthesis Mode ............................................................... 308 - Pattern Detector Register Configurations .................................. 315 - Error Insertion Rates.................................................................. 321
PROPRIETARY AND CONFIDENTIAL
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STANDARD PRODUCT DATA SHEET PMC-1970624 ISSUE 10
PM4351 COMET
COMBINED E1/T1 TRANSCEIVER
Table 69 Table 70 Table 71 Table 72 Table 73 Table 74 Table 75 Table 76 Table 77 Table 78 Table 79 Table 80 Table 81 Table 82 Table 83 Table 84 Table 85 Table 86 Table 87 Table 88 Table 89 Table 90 Table 91 Table 92
- Transmit Output Amplitude ........................................................ 331 - ALOS Detection/Clearance Thresholds ..................................... 340 - Equalization Feedback Frequencies.......................................... 347 - Valid Period................................................................................ 348 - Observing Inputs in Test Mode 0 ............................................... 351 - Controlling Outputs in Test Mode 0............................................ 352 - Boundary Scan Register ............................................................ 354 - Default Settings ......................................................................... 367 - ESF Frame Format .................................................................... 368 - SLC(R)96 Frame Format ............................................................. 369 - SF Frame Format ...................................................................... 370 - T1DM Frame Format ................................................................. 370 - E1 Frame Format....................................................................... 371 - PMON Polling Sequence ........................................................... 372 - ESF FDL Processing ................................................................. 373 - Performance Report Message Structure and Contents ............. 380 - Performance Report Message Structure Notes ......................... 380 - Performance Report Message Contents.................................... 381 - Transmit Waveform Values for T1 Long Haul (LBO 0 dB): ........ 382 - Transmit Waveform Values for T1 Long Haul (LBO 7.5 dB): ..... 383 - Transmit Waveform Values for T1 Long Haul (LBO 15 dB): ...... 384 - Transmit Waveform Values for T1 Long Haul (LBO 22.5 dB): ... 385 - Transmit Waveform Values for T1 Short Haul (0 - 110 ft.): ........ 386 - Transmit Waveform Values for T1 Short Haul (110 - 220 ft.):.... 387
PROPRIETARY AND CONFIDENTIAL
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STANDARD PRODUCT DATA SHEET PMC-1970624 ISSUE 10
PM4351 COMET
COMBINED E1/T1 TRANSCEIVER
Table 93 Table 94 Table 95 Table 96 Table 97 Table 98 Table 99 220 ft.):
- Transmit Waveform Values for T1 Short Haul (220 - 330 ft.): ... 388 - Transmit Waveform Values for T1 Short Haul (330 - 440 ft.): ... 389 - Transmit Waveform Values for T1 Short Haul (440 - 550 ft.): ... 390 - Transmit Waveform Values for T1 Short Haul (550 - 660 ft.): ... 391 - TR62411 Transmit Waveform Values for T1 Long Haul (LBO 0 dB): 392 - TR62411 Transmit Waveform Values for T1 Short Haul (0 - 110 ft.): 393 - TR62411 Transmit Waveform Values for T1 Short Haul (110 - 394
Table 100 - TR62411 Transmit Waveform Values for T1 Short Haul (220 - 330 ft.): 395 Table 101 - TR62411 Transmit Waveform Values for T1 Short Haul (330 - 440 ft.): 396 Table 102 - TR62411 Transmit Waveform Values for T1 Short Haul (440 - 550 ft.): 397 Table 103 - TR62411 Transmit Waveform Values for T1 Short Haul (550 - 660 ft.): 398 Table 104 - Transmit Waveform Values for E1 120 Ohm:............................. 399 Table 105 - Transmit Waveform Values for E1 75 Ohm:............................... 400 Table 106 - RLPS Register Programming....................................................... 401 Table 107 - RLPS Equalizer RAM Table (T1 mode) ..................................... 402 Table 108 - RLPS Equalizer RAM Table (E1 mode) ..................................... 407 Table 109 - RLPS Equalizer Lookup Table for T1 Performance Monitor Mode412 Table 110 - Pseudo-Random Pattern Generation (PS bit = 0) ..................... 415 Table 111 - Repetitive Pattern Generation (PS bit = 1)................................. 416
Table 112 - PMON Counter Saturation Limits (E1 mode)............................. 423
PROPRIETARY AND CONFIDENTIAL
xx
STANDARD PRODUCT DATA SHEET PMC-1970624 ISSUE 10
PM4351 COMET
COMBINED E1/T1 TRANSCEIVER
Table 113 - PMON Counter Saturation Limits (T1 mode) ............................. 423 Table 114 - Boundary Scan Register ............................................................ 433 Table 115 - D.C. Characteristics ................................................................... 439 Table 116 - Microprocessor Read Access (Figure 55) .................................. 442 Table 117 - Microprocessor Write Access (Figure 56) .................................. 444 Table 118 - Transmit Backplane Interface .................................................... 446 Table 119 - Receive Backplane Interface ..................................................... 448 Table 120 - Receive Digital Interface ............................................................ 452 Table 121 - Transmit Digital Interface ........................................................... 453 Table 122 - JTAG Port Interface ................................................................... 455 Table 123 - Ordering Information.................................................................. 458 Table 124 - Thermal Information................................................................... 458
PROPRIETARY AND CONFIDENTIAL
xxi
STANDARD PRODUCT DATA SHEET PMC-1970624 ISSUE 10
PM4351 COMET
COMBINED E1/T1 TRANSCEIVER
PROPRIETARY AND CONFIDENTIAL
xxii
STANDARD PRODUCT DATA SHEET PMC-1970624 ISSUE 10
PM4351 COMET
COMBINED E1/T1 TRANSCEIVER
1
FEATURES * * Monolithic device which integrates software selectable full-featured T1 and E1 framers and T1 and E1 short haul and long haul line interfaces. Meets or exceeds T1 and E1 shorthaul and longhaul network access specifications including ANSI T1.102, T1.403, T1.408, AT&T TR 62411, ITU-T G.703, G.704 as well as ETSI 300-011, CTR-4, CTR-12 and CTR-13. Provides encoding and decoding of B8ZS, HDB3 and AMI line codes. Provides receive equalization, clock recovery and line performance monitoring. Provides transmit jitter attenuation and digitally programmable long haul and short haul line build out. Provides on-board programmable binary sequence generators and detectors for error testing including support for patterns recommended in ITU-T O.151. Provides three full-featured HDLC controllers, each with 128-byte transmit and receive FIFO buffers. Automatically generates and transmits DS-1 performance report messages to ANSI T1.231 and ANSI T1.408 specifications. Compatible with Mitel ST(R)-bus, AT&T CHI(R) and MVIP PCM backplanes, supporting rates of 1.544 Mbit/s, 2.048 Mbit/s, 4.096 Mbit/s, and 8.192 Mbit/s. Up to four COMET devices may be byte-interleaved on a single backplane with no external circuitry. Supports NxDS0 fractional bandwidth backplane. Provides an 8-bit microprocessor bus interface for configuration, control, and status monitoring. Uses line rate system clock. Provides a IEEE P1149.1 (JTAG) compliant test access port (TAP) and controller for boundary scan test. Implemented in a low power 5 V tolerant +3.3 V CMOS technology.
* * * * * * *
* * * * *
PROPRIETARY AND CONFIDENTIAL
1
STANDARD PRODUCT DATA SHEET PMC-1970624 ISSUE 10
PM4351 COMET
COMBINED E1/T1 TRANSCEIVER
* * 1.1
Available in a high density 80-pin MQFP (14 mm by 14 mm) package or an 81-ball CABGA (9 mm by 9 mm) package. Provides a -40C to +85C Industrial temperature operating range.
Receiver section: * Guaranteed T1 signal reception for distances with up to 36 dB of cable attenuation under production test conditions (772 kHz, VDD = 3.069V and 25C) using PIC 22 gauge cable emulation. Guaranteed E1 signal reception for distances with up to 36 dB of cable attenuation under production test conditions (1.024 MHz, VDD = 3.069V and 25C) using PIC 22 gauge cable emulation. Recovers clock and data using a digital phase locked loop for high jitter tolerance. Provides an alternative digital interface for applications without line interface units. Frames to ITU-T G.704 basic and CRC-4 multiframe formatted E1 signals. The framing procedures are consistent ITU-T G.706 specifications. Frames to DSX/DS-1 signals in D4, SF, ESF and SLC(R)96 formats. Frames to TTC JT-G704 multiframe formatted J1 signals. Supports the alternate CRC-6 calculation for Japanese applications. Frames in the presence of and detects the "Japanese Yellow" alarm. Tolerates more than 0.3 UI peak-to-peak, high frequency jitter as required by AT&T TR 62411 and Bellcore TR-TSY-000170. Detects violations of the ANSI T1.403 12.5% pulse density rule over a moving 192-bit window. Provides loss of signal detection as per ITU-T G.775 and ANSI T1.231. Red, Yellow, and AIS alarm detection and integration are according to ANSI T1.231 specifications. Provides programmable in-band loopback activate and deactivate code detection.
*
* * * * * * * * *
*
PROPRIETARY AND CONFIDENTIAL
2
STANDARD PRODUCT DATA SHEET PMC-1970624 ISSUE 10
PM4351 COMET
COMBINED E1/T1 TRANSCEIVER
*
Supports line and path performance monitoring according to AT&T and ANSI specifications. Accumulators are provided for counting ESF CRC-6 errors, framing bit errors, line code violations and loss of frame or change of frame alignment events. Provides ESF bit-oriented code detection and an HDLC/LAPD interface for terminating the ESF facility data link. Supports polled or interrupt-driven servicing of the HDLC interface. Extracts the data link in ESF and T1DM (DDS) modes. Optionally extracts a datalink in the E1 national use bits. Extracts 4-bit codewords from the E1 national use bits as specified in ETS 300 233 Extracts up to three HDLC links from arbitrary time slots to support the Dchannel for ISDN Primary Rate Interfaces and the C-channels for V5.1/V5.2 interfaces. Detects the V5.2 link identification signal. Provides a two-frame elastic store buffer for backplane rate adaptation that performs controlled slips and indicates slip occurrence and direction. Provides DS-1 robbed bit signaling extraction, with optional data inversion, programmable idle code substitution, digital milliwatt code substitution, bit fixing, and two superframes of signaling debounce on a per-channel basis. Frames to the E1 signaling multiframe alignment when enabled and extracts channel associated signaling. Alternatively, a common channel signaling data link may be extracted from timeslot 16. Can be programmed to generate an interrupt on change of signaling state. Provides trunk conditioning which forces programmable trouble code substitution and signaling conditioning on all channels or on selected channels. Provides diagnostic, line loopbacks and per-DS0 line loopback. Provides an integral pattern detector that may be programmed to detect common pseudo-random sequences. The programmed sequence may be detected in the entire frame, or on an NxDS0 basis.
* * * * *
* * *
*
* *
* *
PROPRIETARY AND CONFIDENTIAL
3
STANDARD PRODUCT DATA SHEET PMC-1970624 ISSUE 10
PM4351 COMET
COMBINED E1/T1 TRANSCEIVER
* * 1.2
Provides an integral pattern generator that may be programmed to generate common pseudo-random or repetitive sequences towards the backplane. Provides tristateable single-rail PCM and signaling data outputs for 1.544 Mbit/s, 2.048 Mbit/s, 4.096 Mbit/s or 8.192 Mbit/s backplane buses.
Transmitter section: * * * * * * * Supports transfer of transmitted single rail PCM and signaling data from 1.544 Mbit/s, 2.048 Mbit/s, 4.096 Mbit/s or 8.192 Mbit/s backplane buses. Generates DSX-1 shorthaul and DS-1 longhaul pulses with programmable pulse shape compatible with AT&T, ANSI and ITU requirements. Generates E1 pulses compliant to G.703 recommendations. Provides a digitally programmable pulse shape extending up to 5 transmitted bit periods for custom long haul pulse shaping applications. Provides line outputs which are current limited and may be tristated for protection or in redundant applications. Provides an alternative digital interface for external line interface units. Provides a digital phase locked loop for generation of a low jitter transmit clock complying with all jitter attenuation, jitter transfer and residual jitter specifications of AT&T TR 62411 and ETSI TBR 12 and TBR 13. Provides a FIFO buffer for jitter attenuation and rate conversion in the transmit path. Provides a two-frame payload slip buffer to allow independent backplane and line timing. Provides an integral pattern generator that may be programmed to generate common pseudo-random or repetitive sequences. The programmed sequence may be inserted in the entire frame, or on an NxDS0 basis. Provides an integral pattern detector that may be programmed to detect common pseudo-random or repetitive sequences from the backplane. Transmits G.704 basic and CRC-4 multiframe formatted E1 signals or D4, SF or ESF formatted DSX/DS-1 signals.
* * *
* *
PROPRIETARY AND CONFIDENTIAL
4
STANDARD PRODUCT DATA SHEET PMC-1970624 ISSUE 10
PM4351 COMET
COMBINED E1/T1 TRANSCEIVER
* * * * *
Transmits TTC JT-G704 multiframe formatted J1 signals. Supports the alternate ESF CRC-6 calculation for Japanese applications. Transmits the "Japanese Yellow" alarm. Supports unframed mode and framing bit, CRC, or data link by-pass. Provides signaling insertion, programmable idle code substitution, digital milliwatt code substitution, and data inversion on a per channel basis. Provides trunk conditioning which forces programmable trouble code substitution and signaling conditioning on all channels or on selected channels. Provides minimum ones density through Bell (bit 7), GTE or DDS zero code suppression on a per channel basis. Detects violations of the ANSI T1.403 12.5% pulse density rule over a moving 192-bit window and optionally stuffs ones to maintain minimum ones density. Allows insertion of framed or unframed in-band loopback code sequences. Allows insertion of a data link in ESF or T1DM (DDS) DS-1 modes. Optionally inserts a datalink in the E1 national use bits. Supports 4-bit codeword insertion in the E1 national use bits as specified in ETS 300 233 Inserts up to three HDLC links into arbitrary time slots to support the Dchannel for ISDN Primary Rate Interfaces and the C-channels for V5.1/V5.2 interfaces. Supports transmission of the alarm indication signal (AIS) and the Yellow alarm signal. Supports "Japanese Yellow" alarm generation. Provides ESF bit-oriented code generation.
* * * * * *
* *
PROPRIETARY AND CONFIDENTIAL
5
STANDARD PRODUCT DATA SHEET PMC-1970624 ISSUE 10
PM4351 COMET
COMBINED E1/T1 TRANSCEIVER
2
APPLICATIONS * * * * * * * * * * T1/E1 Wireless Digital Loop Carriers (DLC's) and Cellular Base Stations T1/E1 Internet Access Equipment T1/E1 Channel Service Units (CSU) T1/E1 Frame Relay Interfaces T1/E1 ATM Interfaces T1/E1 Multiplexers (CPE MUX) Digital Private Branch Exchanges (PBX) Digital Access Cross-Connect Systems (DACS) and Electronic DSX CrossConnect Systems (EDSX) ISDN Primary Rate Interfaces (PRI) Test Equipment
PROPRIETARY AND CONFIDENTIAL
6
STANDARD PRODUCT DATA SHEET PMC-1970624 ISSUE 10
PM4351 COMET
COMBINED E1/T1 TRANSCEIVER
3
REFERENCES 1. ANSI - T1.101-1987 - American National Standard for Telecommunications Digital Hierarchy - Timing Synchronization. 2. ANSI - T1.102-1993 - American National Standard for Telecommunications Digital Hierarchy - Electrical Interfaces. 3. ANSI - T1.107-1995 - American National Standard for Telecommunications Digital Hierarchy - Formats Specification. 4. ANSI - T1.231-1993 - American National Standard for Telecommunications Layer 1 In-Service Digital Transmission Performance Monitoring 5. ANSI - T1.403-1995 - American National Standard for Telecommunications Carrier to Customer Installation - DS-1 Metallic Interface Specification. 6. ANSI - T1.408-1990 - American National Standard for Telecommunications Integrated Services Digital Network (ISDN) Primary Rate - Customer Installation Metallic Interfaces Layer 1 Specification. 7. AT&T - PUB 43802 - Digital Multiplexes Requirements and Objectives, July 1982. 8. AT&T - PUB 54016 - Requirements For Interfacing Digital Terminal Equipment To Services Employing The Extended Superframe Format, October 1984. 9. AT&T - TR 62411 - Accunet T1.5 - Service Description and Interface Specification, December 1990. 10. AT&T - TR 62411 - Accunet T1.5 - Service Description and Interface Specification, Addendum 1, March 1991. 11. AT&T - TR 62411 - Accunet T1.5 - Service Description and Interface Specification, Addendum 2, October 1992. 12. AT&T - Interface Specification - Concentration Highway Interface November 1990. 13. Bellcore - Digital Cross-Connect System Requirements and Objectives, TR-TSY-000170, Issue 1, November 1985. 14. Bellcore - Extended Superframe format (ESF),TR-TSY-000194, Issue 1, December 1987
PROPRIETARY AND CONFIDENTIAL
7
STANDARD PRODUCT DATA SHEET PMC-1970624 ISSUE 10
PM4351 COMET
COMBINED E1/T1 TRANSCEIVER
15. ETSI - ETS 300 011 - Integrated Services Digital Network (ISDN); Primary Rate User-Network Interface Layer 1 Specification and Test Principles, April 1992. 16. ETSI - ETS 300 011 A1 - Integrated Services Digital Network (ISDN); Primary Rate User-Network Interface Layer 1 Specification and Test Principles, December 1992. 17. ETSI - ETS 300 011 A2 - Integrated Services Digital Network (ISDN); Primary Rate User-Network Interface Layer 1 Specification and Test Principles, March 1996. 18. ETSI - ETS 300 166 - Transmission and Multiplexing (TM); Physical and Electrical Characteristics of Hierarchical Digital Interfaces for Equipment Using the 2 048 kbit/s - based Plesiochronous or Synchronous Digital Hierarchies, August 1993. 19. ETSI - ETS 300 233 - Integrated Services Digital Network (ISDN); Access Digital Section for ISDN Primary Rate, May 1994. 20. ETSI - ETS 300 324-1 - Signaling Protocols and Switching (SPS); V interfaces at the Digital Local Exchange (LE) V5.1 Interface for the Support of Access Network (AN) Part 1: V5.1 Interface Specification, February 1994. 21. ETSI - ETS 300 347-1 - Signaling Protocols and Switching (SPS); V Interfaces at the Digital Local Exchange (LE) V5.2 Interface for the Support of Access Network (AN) Part 1: V5.2 Interface Specification, September 1994. 22. ETSI - CTR 4 - Integrated Services Digital Network (ISDN); Attachment requirements for terminal equipment to connect to an ISDN using ISDN primary rate access, November 1995. 23. ETSI - CTR 12 - Business Telecommunications (BT); Open Network Provision (ONP) technical requirements; 2 048 kbit/s digital unstructured leased lines (D2048U) Attachment requirements for terminal equipment interface, December 1993. 24. ETSI - CTR 13 - Business Telecommunications (BTC); 2 048 kbit/s digital structured leased lines (D2048S); Attachment requirements for terminal equipment interface, January 1996. 25. FCC Rules - Part 68.308 - Signal Power Limitations 26. ITU-T - Recommendation G.703 - Physical/Electrical Characteristics of Hierarchical Digital Interface, Geneva, 1991.
PROPRIETARY AND CONFIDENTIAL
8
STANDARD PRODUCT DATA SHEET PMC-1970624 ISSUE 10
PM4351 COMET
COMBINED E1/T1 TRANSCEIVER
27. ITU-T - Recommendation G.704 - Synchronous Frame Structures Used at Primary Hierarchical Levels, July 1995. 28. ITU-T - Recommendation G.706 - Frame Alignment and CRC Procedures Relating to G.704 Frame Structures, 1991. 29. ITU-T - Recommendation G.732 - Characteristics of Primary PCM Multiplex Equipment Operating at 2048 kbit/s, 1993. 30. ITU-T - Recommendation G.711 - Pulse Code Modulation (PCM) of Voice Frequencies, 1993. 31. ITU-T - Recommendation G.775 - Loss of Signal (LOS), November 1994. 32. ITU-T Recommendation G.802, - Interworking Between Networks Based on Different Digital Hierarchies and Speech Encoding Laws, 1993. 33. ITU-T Recommendation G.823, - The Control of Jitter and Wander Within Digital Networks Which are Based on the 2048 kbit/s Hierarchy, 1993. 34. ITU-T Recommendation G.964, - V-Interfaces at the Digital Local Exchange (LE) - V5.1 Interface (Based on 2048 kbit/s) for the Support of Access Network (AN), June 1994. 35. ITU-T Recommendation G.965, - V-Interfaces at the Digital Local Exchange (LE) - V5.2 Interface (Based on 2048 kbit/s) for the Support of Access Network (AN), March 1995. 36. ITU-T - Recommendation I.431 - Primary Rate User-Network Interface - Layer 1 Specification, 1993. 37. ITU-T Recommendation O.151, - Error Performance Measuring Equipment For Digital Systems at the Primary Bit Rate and Above, 1988. 38. ITU-T Recommendation O.152 - Error Performance Measuring Equipment for Bit Rates of 64 kbit/s and N X 64 kbit/s, October 1992 39. ITU-T Recommendation O.153 - Basic Parameters for the Measurement of Error Performance at Bit Rates below the Primary Rate, October 1992. 40. TTC Standard JT-G703 - Physical/Electrical Characteristics of Hierarchical Digital Interfaces, 1995. 41. TTC Standard JT-G704 - Frame Structures on Primary and Secondary Hierarchical Digital Interfaces, 1995.
PROPRIETARY AND CONFIDENTIAL
9
STANDARD PRODUCT DATA SHEET PMC-1970624 ISSUE 10
PM4351 COMET
COMBINED E1/T1 TRANSCEIVER
42. TTC Standard JT-G706 - Frame Synchronization and CRC Procedure 43. TTC Standard JT-I431 - ISDN Primary Rate User-Network Interface Layer 1 Specification, 1995. 44. Nippon Telegraph and Telephone Corporation - Technical Reference for HighSpeed Digital Leased Circuit Services, Third Edition, 1990. 45. GO-MVIP - Multi-Vendor Integration Protocol, MVIP-90 Release 1.1, 1994.
PROPRIETARY AND CONFIDENTIAL
10
STANDARD PRODUCT DATA SHEET PMC-1970624 ISSUE 10
PM4351 COMET
COMBINED E1/T1 TRANSCEIVER
4
APPLICATION EXAMPLE Figure 1 - Wireless Base Station Application
TOCTL/TQUAD/ QDSX EQUAD PM8313 D3MX or PM5342 SPECTRA Basestation Switch Fabric TOCTL/TQUAD/ QDSX EQUAD TOCTL/TQUAD/ QDSX EQUAD TOCTL/TQUAD/ QDSX EQUAD
T1/E1/J1 Longhaul/ Shorthaul LIU
Software Selectable T1/E1/J1 Framer
MVIP
Tx/Rx RF Subsystem Intel or Motorola P
PM4351 COMET
T1/E1/J1 Longhaul/ Shorthaul LIU Software Selectable T1/E1/J1 Framer
MVIP
Low Power 3.3v Power Supply
PM4351 COMET
CDMA/TDMA/GSM
DS3 or Fibre Optics
Base Station Controller
Base Transceiver Station
q q q
Public Switched Telephone Network
COMET provides a complete physical layer solution for Basestation designs, while the PM4314 QDSX, the PM6344 EQUAD, the and PM4388 TOCTL provide high density multi-channel solutions for the Basestation Controller
PROPRIETARY AND CONFIDENTIAL
11
STANDARD PRODUCT DATA SHEET PMC-1970624 ISSUE 10
PM4351 COMET
COMBINED E1/T1 TRANSCEIVER
Figure 2
- V5.1 Interface Application
Switch Fabric PM5342 PM5362 SPECTRA TUPP+ 155
PM4314 PM6344 QDSX EQUAD PM4314 PM6344 QDSX EQUAD PM4314 PM6344 QDSX EQUAD PM4314 PM6344 QDSX EQUAD
V5.1 Interface
q q q
LIU PM7364 FREEDM Processor
Framer HDLC HDLC HDLC
Line Card Line Card Line Card
q q q
Central Office Switch
STM-1
PM4351 COMET
Intel or Motorola P
Line Card
Subscribers
Low Power 3.3v Power Supply
Pedestal-Mount Digital Loop Carrier
COMET used in conjunction with PM6344 EQUAD and PM7366 FREEDM-8 to provide a complete V5.1 solution for both the Access Network and the Central Office
PROPRIETARY AND CONFIDENTIAL
12
STANDARD PRODUCT DATA SHEET PMC-1970624 ISSUE 10
PM4351 COMET
COMBINED E1/T1 TRANSCEIVER
5
BLOCK DIAGRAM
TXR IN G[2:1] XCLK / VCLK
TXTIP[2 :1]
RSYNC
TCL KO
RVREF
RXRIN G
TVR EF
RXTIP
TD A T
TFP
D[7:0] A[8:0] RDB W RB CSB ALE RS TB IN TB M PIF MicroProcessor Inte rface
XLPG Transm it LIU
RLPS Receive LIU
TJAT Tra nsm it Digita l Jitter Attenuator
CSD Clock Synthesis and Distribution
CDRC Clock and Data Recovery
TOPS Timing Options
RJAT Receive Digita l Jitter Attenuator
TD O TD I TC K TMS TR S TB JTAG Test Access Port XIBC Inband Loopback Code G enerator PRG D 1/2 Patte rn Generator/ Detector XPDE Pulse Density Enforcer
T1-XBAS/ E1-TRAN BasicTransm itte r: Frame Generation, Alarm Insertio n, XBO C Signaling Insertion, Bit O riented Trunk Conditioning Code G enerator
RDA T
RCLKI
PDVD Pulse Density Viola tion Detector
TC LKI
TPSC Per-DS0 Serial Controller FRAM Framing RAM
IBCD Inband Loopback Code Detector
FRM R Frame Alignm ent, Alarm Extraction
PM ON Perform ance Monitor Counters
ALM I Alarm Integrator
RBOC Bit Oriented Code Detector
TDPR#3 HDLC Tran smitter TDPR#2 HDLC Tran sm itter TDPR#1 HDLC Tran sm itter RXELST Elastic Store
RDLC#3 HDLC Receiver RDLC#2 HDLC Receiver RDLC#1 HDLC Receiver
TXELST Elastic Store
BTIF Backplane Tra nsm it Inte rface
PRGD 1/2 Patte rn Generator / Detector
RPSC Per-DS0 Serial Controller
BRIF Backplane Receive Inte rface
E1/T1SIG X Signaling Extractor
BTS IG
BTFP
BTPC M
BTC LK
BRCLK
BRPCM
PROPRIETARY AND CONFIDENTIAL
13
BRS IG
BRFP
STANDARD PRODUCT DATA SHEET PMC-1970624 ISSUE 10
PM4351 COMET
COMBINED E1/T1 TRANSCEIVER
6
DESCRIPTION The PM4351 Combined E1/T1 Transceiver (COMET) is a feature-rich monolithic integrated circuit suitable for use in long haul and short haul T1 and E1 systems with a minimum of external circuitry. The COMET is software configurable, allowing feature selection without changes to external wiring. Analog circuitry is provided to allow direct reception of long haul E1 and T1 compatible signals with up to 36 dB cable loss (at 1.024 MHz in E1 mode) or up to 36 dB cable loss (at 772 kHz in T1 mode) using a minimum of external components. Typically, only line protection, a transformer and a line termination resistor are required. Digital line inputs are provided for applications not requiring a physical T1 or E1 interface. The COMET recovers clock and data from the line and frames to incoming data. In T1 mode, it can frame to several DS-1 signal formats: SF, ESF, T1DM (DDS) and SLC(R)96. In E1 mode, the COMET frames to basic G.704 E1 signals and CRC-4 multiframe alignment signals, and automatically performs the G.706 interworking procedure. AMI, HDB3 and B8ZS line codes are supported. The COMET supports detection of various alarm conditions such as loss of signal, pulse density violation, Red alarm, Yellow alarm, and AIS alarm in T1 mode and loss of signal, loss of frame, loss of signaling multiframe and loss of CRC multiframe in E1 mode. The COMET also supports reception of remote alarm signal, remote multiframe alarm signal, alarm indication signal, and time slot 16 alarm indication signal in E1 mode. The presence of Yellow and AIS patterns in T1 mode and remote alarm and AIS patterns in E1 mode is detected and indicated. In T1 mode, the COMET integrates Yellow, Red, and AIS alarms as per industry specifications. In E1 mode, the COMET integrates Red and AIS alarms. Performance monitoring with accumulation of CRC-6 errors, framing bit errors, line code violations, and loss of frame events is provided in T1 mode. In E1 mode, CRC-4 errors, far end block errors, framing bit errors, and line code violation are monitored and accumulated. The COMET provides three receive HDLC controllers for the detection and termination of messages on the ESF facility data link (T1) or national use bits (E1) and in any arbitrary time slot (T1 or E1). In T1 mode, the COMET also detects the presence of in-band loop back codes and ESF bit oriented codes. Detection and optional debouncing of the 4-bit Sa-bit codewords defined in ITUT G.704 and ETSI 300-233 is supported. An interrupt may be generated on any change of state of the Sa codewords.
PROPRIETARY AND CONFIDENTIAL
14
STANDARD PRODUCT DATA SHEET PMC-1970624 ISSUE 10
PM4351 COMET
COMBINED E1/T1 TRANSCEIVER
Dual (transmit and receive) elastic stores for slip buffering and rate adaptation to backplane timing are provided, as is a signaling extractor that supports signaling debounce, signaling freezing, idle code substitution, digital milliwatt tone substitution, data inversion, and signaling bit fixing on a per-channel basis. Receive side data and signaling trunk conditioning is also provided. In T1 mode, the COMET generates framing for SF, ESF and T1DM (DDS) formats. In E1 mode, the COMET generates framing for a basic G.704 E1 signal. The signaling multiframe alignment structure and the CRC multiframe structure may be optionally inserted. Framing can be optionally disabled. Internal analog circuitry allows direct transmission of long haul and short haul T1 and E1 compatible signals using a minimum of external components. Typically, only line protection, a transformer and an optional line termination resistor are required. Digitally programmable pulse shaping allows transmission of DSX-1 compatible signals up to 655 feet from the cross-connect, E1 short haul pulses into 120 ohm twisted pair or 75 ohm coaxial cable, E1 long haul pulses into 120 ohm twisted pair as well as long haul DS-1 pulses into 100 ohm twisted pair with integrated support for LBO filtering as required by the FCC rules. In addition, the programmable pulse shape extending over 5-bit periods allows customization of short haul and long haul line interface circuits to application requirements. Digital line inputs and outputs are provided for applications not requiring a physical T1 or E1 interface. In the transmit path, the COMET supports signaling insertion, idle code substitution, digital milliwatt tone substitution, data inversion, and zero code suppression on a per-channel basis. Zero code suppression may be configured to Bell (bit 7), GTE, or DDS standards, and can also be disabled. Transmit side data and signaling trunk conditioning is also provided. Signaling bit transparency from the backplane may be enabled. The COMET provides three transmit HDLC controllers. These controllers may be used for the transmission of messages on the ESF data link (T1) or national use bits (E1) and in any time slot. In T1 mode, the COMET can be configured to generate in-band loop back codes and ESF bit oriented codes. In E1 mode, transmission of the 4-bit Sa codewords defined in ITU-T G.704 and ETSI 300233 is supported. The COMET provides optional jitter attenuation in both the transmit and receive directions. The COMET provides both a parallel microprocessor interface for controlling the operation of the device and serial PCM interfaces that allow backplane rates from 1.544 Mbit/s to 8.192 Mbit/s to be directly supported. Up to four COMET devices can be multiplexed on a byte-interleaved basis on a common bus with
PROPRIETARY AND CONFIDENTIAL
15
STANDARD PRODUCT DATA SHEET PMC-1970624 ISSUE 10
PM4351 COMET
COMBINED E1/T1 TRANSCEIVER
no additional arbitration logic. The COMET supports the Mitel ST(R) bus, AT&T CHI(R) and MVIP standards.
PROPRIETARY AND CONFIDENTIAL
16
STANDARD PRODUCT DATA SHEET PMC-1970624 ISSUE 10
PM4351 COMET
COMBINED E1/T1 TRANSCEIVER
7
PIN DIAGRAMS The COMET is packaged in an 80-pin metric plastic quad flat pack (MQFP) package having a body size of 14 mm by 14 mm and a pin pitch of 0.65 mm. Figure 3 PM4351-RI COMET Pin Diagram
TXRING2 TXTIP 2 TA VS 3 TAVD 2 TXTIP 1 TXRING1 RAVD2 RXRING RXT IP 64 63 RAVS 1 RAVD1 62 61 AT B QAVD RAVS 2 TAVD 3 TVREF TA VS 2 TAVD 4 TA VS 4 QAV S 70 69
80 79 78 77
76 75
74 73 72 71
68 67 66 65
TAVD1 TA VS1 XCLK TCLK I TCLKO TD AT TF P VDDO2 VSSO 2 BTC LK BTPC M BTSIG BTF P VDDI2 VSSI2 TC K TM S TDI TDO TR ST B
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
60 59 58 57 56 55 54 53 52
RVREF PIO TRIM F RDA T RCLKI RSYNC BRCLK VDDO1 VSSO 1 BRPCM BRSIG BRFP VDDI1 VSSI1 BIA S ALE A[8] A[7] A[6] A[5]
PM4351-RI
(TOP VIEW )
51 50 49 48 47 46 45 44 43 42 41
21 22 23 24
25 26 27 28 29
30 31 32 33 34 35
36 37 38 39 A[2] A[3]
CSB RS TB RDB W RB INTB D[0] D[1]
D[2] D[3] VDDO3 VSSO 3
D[4] D[5]
D[6] D[7] A[0] A[1]
PROPRIETARY AND CONFIDENTIAL
17
A[4]
40
STANDARD PRODUCT DATA SHEET PMC-1970624 ISSUE 10
PM4351 COMET
COMBINED E1/T1 TRANSCEIVER
The COMET is also available in an 81 pin Chip Array Ball Grid Array (CABGA) package having a body size of 9 mm by 9 mm and a pin pitch of 0.8 mm. Figure 4 PM4351-NI COMET Pin Diagram
(Bottom View)
9 A B C RAVD1 PIO RSYNC 8 RXRING RAVS1 TRIMF 7 RAVD2 RAVS2 RXTIP 6 QAVD ATB TAVS4 5 TAVD4 TAVD3 TXRING 1 D E F G H J RCLKI BRPCM VSSI2 ALE A[8] A[5] 9 BRCLK RDAT VDDI2 BIAS A[6] A[3] 8 RVREF VSSO2 BRSIG A[7] A[2] D[7] 7 QAVS VDDO2 BRFP A[4] D[6] A[0] 6 TXTIP1 NC D[5] D[4] A[1] VSSO3 5 4 TVREF TAVD2 TXRING 2 VSSO1 BTFP D[3] VDDO3 D[2] D[1] 4 3 TAVS2 TAVS3 XCLK/ VCLK BTCLK BTSIG TRSTB RDB D[0] INTB 3 VDDO1 TMS VDDI1 TDI RSTB WRB 2 TFP BTPCM TCK VSSI1 TDO CSB 1 D E F G H J 2 TXTIP2 TAVS1 TDAT 1 TAVD1 TCLKI TCLKO A B C
PROPRIETARY AND CONFIDENTIAL
18
STANDARD PRODUCT DATA SHEET PMC-1970624 ISSUE 10
PM4351 COMET
COMBINED E1/T1 TRANSCEIVER
8
PIN DESCRIPTION Table 1
Pin Name
- Backplane Transmit Interface (4 pins)
Type Pin No. -RI -NI D3 Backplane Transmit Clock (BTCLK). In synchronous backplane applications, the BTCLK input may be a 1.544 MHz, 2.048 MHz, 3.088 MHz, 4.096 MHz, 8.192 MHz or 16.384 MHz clock with optional gapping for adaptation from nonuniform system clocks. BTCLK can be configured as a line-rate output, in which case it is referenced to TCLKI or the receive recovered clock (loop timed). In T1 NxDS0 mode, BTCLK is gapped during the framing bit position and optionally for between 1 and 23 DS0 channels in the backplane data stream. In E1 NxDS0 mode, BTCLK is gapped optionally for between 1 and 31 time slots in the backplane data stream. When BTCLK is configured as an input, byte-interleaved backplanes are supported. BTCLK may be configured to be active on either its rising or falling edge. BTPCM and BTSIG are sampled on the active edge of BTCLK. Depending on its configuration, BTFP is either sampled or updated on the selected active edge of BTCLK. After a reset, BTCLK is configured as an input. Function
BTCLK
I/O
10
PROPRIETARY AND CONFIDENTIAL
19
STANDARD PRODUCT DATA SHEET PMC-1970624 ISSUE 10
PM4351 COMET
COMBINED E1/T1 TRANSCEIVER
Pin Name
Type
Pin No. -RI -NI E4
Function
BTFP
I/O
13
Backplane Transmit Frame Pulse (BTFP). When BTFP is configured as an input, it is used to frame align the transmitter to the system backplane. T1 mode: If only frame alignment is required, a pulse at least one BTCLK cycle wide must be provided on BTFP at multiples of 193 bit periods. If superframe alignment is required, transmit superframe alignment must be enabled, and BTFP must be brought high for at least one BTCLK cycle to mark bit 1 of frame 1 of every 12-frame or 24-frame superframe. E1 mode: If basic frame alignment only is required, a pulse at least one BTCLK cycle wide must be provided on BTFP at multiples of 256 bit periods. If multiframe alignment is required, transmit multiframe alignment must be enabled, and BTFP must be brought high to mark bit 1 of frame 1 of every 16-frame signaling multiframe and brought low following bit 1 of frame 1 of every 16frame CRC multiframe. This mode allows both multiframe alignments to be independently controlled using the single BTFP signal. Note that if the signaling and CRC multiframe alignments are coincident, BTFP must pulse high for one BTCLK cycle every 16 frames. When BTFP is configured as an output (only valid when the transmit backplane clock rate is no greater than 2.048 MHz), transmit frame alignment is derived internally and BTFP is updated on the configured active edge of BTCLK. BTFP pulses high for one cycle to indicate the first bit of each frame or multiframe, as optioned. After a reset, BTFP is configured as an input.
BTPCM
Input
11
E1
Backplane Transmit PCM Data (BTPCM). The non-return to zero, digital data stream to be transmitted is input on this pin. BTPCM may present a 1.544 Mbit/s, 2.048 Mbit/s or sub-rate NxDS0 data stream or may present a byte-interleaved 4.096 Mbit/s or 8.192 Mbit/s multiplexed data stream. The bit alignment of BTPCM relative to BTFP is configurable. Two mappings of a DS-1 into a 2.048 Mbit/s format are defined: every fourth timeslot unused and 24 contiguous timeslots. The BTPCM signal is sampled on the configured active edge of BTCLK.
BTSIG
Input
12
E3
Backplane Transmit Signaling (BTSIG). The BTSIG input signal contains the signaling bits for each channel in the transmit data frame, repeated for the entire superframe. Each channel's signaling bits are in bit locations 5, 6, 7 and 8 of the channel and are channel-aligned with the BTPCM data stream. The BTSIG signal is sampled on the configured active edge of BTCLK.
PROPRIETARY AND CONFIDENTIAL
20
STANDARD PRODUCT DATA SHEET PMC-1970624 ISSUE 10
PM4351 COMET
COMBINED E1/T1 TRANSCEIVER
Table 2
Pin Name
- Backplane Receive Interface (4 pins)
Type Pin No. -RI -NI D8 Backplane Receive Clock (BRCLK). When BRCLK is configured as an input and the elastic store is enabled, BRCLK may be either a 1.544 MHz, 2.048 MHz, 3.088 MHz, 4.096 MHz, 8.192 MHz or 16.384 MHz clock with optional gapping for adaptation to non-uniform backplane data streams. When BRCLK is configured as a output, it can be either a 1.544 MHz or 2.048 MHz clock derived from the recovered line rate timing (available on RSYNC), with optional jitter attenuation. In T1 NxDS0 mode, BRCLK is gapped during the framing bit position and optionally for between 1 and 23 DS0 channels in the backplane data stream. In E1 NxDS0 mode, BRCLK is gapped optionally for between 1 and 31 time slots in the backplane data stream. Either the rising or falling edge of BRCLK may be configured as the active edge. BRPCM and BRSIG are updated on the active edge of BRCLK. When BRFP is configured as an input, it is sampled on the active edge of BRCLK. When BRFP is configured as an output, it is updated on the active edge of BRCLK. After a reset, BRCLK is configured as an input. Function
BRCLK
I/O
54
PROPRIETARY AND CONFIDENTIAL
21
STANDARD PRODUCT DATA SHEET PMC-1970624 ISSUE 10
PM4351 COMET
COMBINED E1/T1 TRANSCEIVER
Pin Name
Type
Pin No. -RI -NI F6
Function
BRFP
I/O
49
Backplane Receive Frame Pulse (BRFP). When BRFP is configured as an output, it indicates the frame alignment of BRPCM and BRSIG. BRFP is generated on the active edge of BRCLK. T1 mode: If basic frame alignment is desired, BRFP pulses high for one BRCLK cycle during bit 1 of each 193-bit frame. Optionally, BRFP may pulse high every second frame to ease the identification of data link bits. If superframe alignment is desired, BRFP pulses high for one BRCLK cycle during bit 1 of frame 1 of every 12-frame or 24-frame superframe. Optionally, BRFP may pulse high every second superframe to ease the conversion between SF and ESF. E1 mode: If basic frame alignment is desired, BRFP pulses high for one BRCLK cycle during bit 1 of each 256-bit frame. Optionally, BRFP may pulse high every second frame to ease the identification of NFAS frames. If multiframe alignment is desired, BRFP transitions high to mark bit 1 of frame 1 of every 16-frame signaling multiframe and transitions low following bit 1 of frame 1 of every 16-frame CRC multiframe. Note that if the signaling and CRC multiframe alignments are coincident, BRFP pulses high for one BRCLK cycle every 16 frames. When BRFP is configured as an input, it is used to frame align the receive data to the backplane frame alignment. When frame alignment is required, a pulse at least one BRCLK cycle wide must be provided on BRFP a maximum of once every frame (193 bit periods in T1 mode or 256 bit periods in E1 mode). BRFP is sampled on the active edge of BRCLK. After a reset, BRFP is configured as an input.
BRPCM
Output with Tristate
51
E9
Backplane Receive PCM Data (BRPCM). BRPCM contains the recovered data stream passed through the elastic store, signaling extractor and per-DS0 serial controller. When the receive elastic store is not bypassed, the BRPCM stream is aligned to the backplane input timing. When BRCLK is either 4.096 MHz, 8.192 MHz or 16.384 MHz, BRPCM can be tristated and is only active during programmable timeslots. This allows byte interleaving of PCM data streams from up to 4 COMET devices with no external logic. After a reset, BRPCM is high impedance. BRPCM is updated on the active edge of BRCLK.
PROPRIETARY AND CONFIDENTIAL
22
STANDARD PRODUCT DATA SHEET PMC-1970624 ISSUE 10
PM4351 COMET
COMBINED E1/T1 TRANSCEIVER
Pin Name
Type
Pin No. -RI -NI F7
Function
BRSIG
Output with Tristate
50
Backplane Receive Signaling (BRSIG). BRSIG contains the extracted signaling bits for each channel in the frame, repeated for the entire superframe. Each channel's signaling bits are valid in bit locations 5, 6, 7 and 8 of the channel and are channel-aligned with the BRPCM data stream. When the RXELST is not by-passed, the BRSIG stream is aligned to the backplane input timing. When BRCLK is either 4.096 MHz, 8.192 MHz or 16.384 MHz, BRSIG can be tristated and is only active during programmable timeslots to allow byte interleaving of signaling data streams from up to 4 COMET devices with no external logic. After a reset, BRSIG is high impedance. BRSIG is updated on the active edge of BRCLK.
Table 3
Pin Name
- Transmit Line Interface (6 pins)
Type Pin No. -RI -NI D5 A2 Transmit Analog Positive Pulse (TXTIP1 and TXTIP2). When the transmit analog line interface is enabled, the TXTIP1 and TXTIP2 analog outputs drive the transmit line pulse signal through an external matching transformer. Both TXTIP1 and TXTIP2 are normally connected to the positive lead of the transformer primary. Two outputs are provided for better signal integrity and should be shorted together on the board. After a reset, TXTIP1 and TXTIP2 are high impedance. The HIGHZ bit of the XLPG Line Driver Configuration register (address 0F0H) must be programmed to logic 0 to remove the high impedance state. Function
TXTIP1 TXTIP2
Analog Output
73 79
TXRING1 TXRING2
Analog Output
72 80
C5 C4
Transmit Analog Negative Pulse (TXRING1 and TXRING2). When the transmit analog line interface is enabled, the TXRING1 and TXRING2 analog outputs drive the transmit line pulse signal through an external matching transformer. Both TXRING1 and TXRING2 are normally connected to the negative lead of the transformer primary. Two outputs are provided for better signal integrity and should be shorted together on the board. After a reset, TXRING1 and TXRING2 are high impedance. The HIGHZ bit of the XLPG Line Driver Configuration register (address 0F0H) must be programmed to logic 0 to remove the high impedance state.
TDAT
Digital Output
6
C2
Transmit Digital PCM Data (TDAT). When the transmit digital line interface is enabled, the TDAT output provides the line side NRZ PCM transmit data. This mode may be used in applications not requiring a physical T1/E1 interface (e.g. interfacing to HDSL transceivers). TDAT is updated on the either the rising or falling (default) edge of TCLKO.
PROPRIETARY AND CONFIDENTIAL
23
STANDARD PRODUCT DATA SHEET PMC-1970624 ISSUE 10
PM4351 COMET
COMBINED E1/T1 TRANSCEIVER
Pin Name
Type
Pin No. -RI -NI D1
Function
TFP
Digital Output
7
Transmit Digital Frame Pulse (TFP). When the transmit digital line interface is enabled, the TFP output indicates frame alignment of the line side transmitted PCM stream (TDAT). This mode may be used in applications not requiring a physical T1/E1 interface (e.g. interfacing to HDSL transceivers). TFP is updated on the either the rising or falling (default) edge of TCLKO.
Table 4
Pin Name
- Receive Line Interface (4 pins)
Type Pin No. -RI -NI C7 Receive Analog Positive Pulse (RXTIP). When the analog receive line interface is enabled, RXTIP samples the received line pulse signal from an external isolation transformer. RXTIP is normally connected directly to the positive lead of the receive transformer secondary. Function
RXTIP
Analog Input
63
RXRING
Analog Input
64
A8
Receive Analog Negative Pulse (RXRING). When the analog receive line interface is enabled, RXRING samples the received line pulse signal from an external isolation transformer. RXRING is normally connected directly to the negative lead of the receive transformer secondary.
RDAT
Input
57
E8
Receive Digital Line Data (RDAT). When the digital receive interface is enabled, the RDAT input samples the line side recovered NRZ PCM data stream. This mode may be used in applications not requiring a physical T1/E1 interface (e.g. interfacing to HDSL transceivers). In digital mode, clock and data recovery is disabled. RDAT is sampled on the rising (default) or falling edge of RCLKI.
RCLKI
Input
56
D9
Receive Digital Line Clock (RCLKI). When the digital receive line interface is enabled, the externally recovered line rate clock must be provided on RCLKI. This mode may be used in applications not requiring a physical T1/E1 interface (e.g. interfacing to HDSL transceivers). RCLKI samples the receive PCM stream (RDAT) on its rising (default) or falling edge.
Table 5
Pin Name
- Timing Options Control (5 pins)
Type Pin No. -RI -NI B9 Programmable I/O. PIO is an input/output pin controlled by a COMET register bit. As an output, the PIO bit can, under software control, be used to configure external circuitry dependent upon the mode of the COMET device. As an input, the state of the PIO pin can be read via a register bit. Function
PIO
I/O
59
PROPRIETARY AND CONFIDENTIAL
24
STANDARD PRODUCT DATA SHEET PMC-1970624 ISSUE 10
PM4351 COMET
COMBINED E1/T1 TRANSCEIVER
Pin Name
Type
Pin No. -RI -NI C1
Function
TCLKO
Output
5
Transmit Clock Output (TCLKO). TCLKO is a clock at the transmit line rate and may be used by external circuits as a transmit clock reference. When the digital transmit line interface is enabled, TDAT and TFP are updated on the either the rising or falling (default) edge of TCLKO.
RSYNC
Output
55
C9
Recovered Clock Synchronization Signal (RSYNC). This output signal is the dejittered recovered receiver line rate clock (1.544 or 2.048 MHz) or, optionally, the recovered clock synchronously divided by 193 (T1 mode) or 256 (E1 mode) to create a 8 kHz timing reference signal. When 8 kHz, the RSYNC phase is independent of frame alignment and is not affected by framing events. When the COMET is in a loss of signal state, RSYNC is derived from the XCLK input or, optionally, is held high.
TCLKI
Input
4
B1
Transmit Clock Reference (TCLKI). TCLKI may be used as a reference for the transmit line rate generation. TCLKI may be any multiple of 8 kHz (N x 8 kHz, where 1N256) so long as TCLKI has minimal jitter when divided down to 8 kHz. When the TCLKI frequency differs from the transmit line rate, the transmit jitter attenuation block (TJAT) must be enabled to attenuate jitter on the transmit clock in accordance with AT&T TR-62411 and ETS 300 011. When the TCLKI frequency is the same as the transmit line rate, TCLKI is optionally jitter attenuated by the TJAT in accordance with AT&T TR-62411 and ETS 300 011. When TCLKI jitter attenuation is enabled, the TCLKI frequency should be programmed into the TJAT Jitter Attenuation Divider N1 Control register. The COMET may be configured to ignore the TCLKI input and utilize BTCLK or the receive recovered clock instead.
XCLK /
Input
3
C3
Crystal Clock Input (XCLK). This signal provides a stable, global timing reference for the COMET internal circuitry via an internal clock synthesizer. XCLK is a nominally jitter-free 50% duty cycle clock at 1.544 MHz in T1 mode and 2.048 MHz in E1 mode. In T1 mode, a 2.048 MHz clock may be used as a reference. When used in this way, however, the intrinsic jitter specifications to AT&T TR62411 may not be met.
VCLK
Vector Clock (VCLK). The VCLK signal is used during COMET production test to verify internal functionality.
Table 6
Pin Name
- Analog Support Circuitry (4 pins)
Type Pin No. -RI -NI B6 Analog Test Bus (ATB). Reserved for COMET production test. This pin must be connected to an analog ground for normal operation. Function
ATB
Analog I/O
68
PROPRIETARY AND CONFIDENTIAL
25
STANDARD PRODUCT DATA SHEET PMC-1970624 ISSUE 10
PM4351 COMET
COMBINED E1/T1 TRANSCEIVER
Pin Name
Type
Pin No. -RI -NI A4
Function
TVREF
Analog I/O
76
Transmit Voltage Reference (TVREF). This pin is reserved for a precision analog voltage or current reference.
RVREF
Analog I/O
60
D7
Receive Voltage Reference (RVREF). This pin is reserved for a precision analog voltage or current reference. This pin must be connected to an external RC network consisting of a 100 kohm resistor connected in parallel with a 10 nF capacitor to analog ground.
TRIMF
Input
58
C8
Trim Fuse. This pin is reserved for production purposes. The TRIMF signal is used during COMET production test to control the trimming of fuses. This pin must be tied low for normal operation.
Table 7
Pin Name
- JTAG (IEEE 1149.1) Boundary Scan Test Interface (5 pins)
Type Pin No. -RI -NI F1 Test Clock (TCK). The test clock (TCK) signal provides timing for test operations that are carried out using the IEEE P1149.1 test access port. Function
TCK
Input
16
TMS
Input
17
E2
Test Mode Select (TMS). The test mode select (TMS) signal controls the test operations that are carried out using the IEEE P1149.1 test access port. TMS is sampled on the rising edge of TCK. TMS has an integral pull-up resistor.
TDI
Input
18
G2
Test Data Input (TDI). The test data input (TDI) signal carries test data into the COMET via the IEEE P1149.1 test access port. TDI is sampled on the rising edge of TCK. TDI has an integral pull-up resistor.
TDO
Output with Tristate
19
H1
Test Data Output (TDO). The test data output (TDO) signal carries test data out of the COMET via the IEEE P1149.1 test access port. TDO is updated on the falling edge of TCK. TDO is a tristate output which is tristated except when scanning of data is in progress.
TRSTB
Input
20
F3
Active Low Test Reset (TRSTB). The test reset (TRSTB) signal provides an asynchronous COMET test access port reset via the IEEE P1149.1 test access port. TRSTB is a Schmitt triggered input with an integral pull-up resistor. The JTAG TAP controller must be initialized when the COMET is powered up. If the JTAG port is not used, TRSTB should be connected to the RSTB input.
Table 8
Pin Name
- Microprocessor Interface (23 pins)
Type Pin No. -RI -NI J1 Active Low Chip Select (CSB). CSB must be low to enable COMET register accesses. CSB must go high at least once after power up to clear internal test modes. If CSB is not used, it should be tied to an inverted version of RSTB, in which case, RDB and WRB determine register accesses. Function
CSB
Input
21
PROPRIETARY AND CONFIDENTIAL
26
STANDARD PRODUCT DATA SHEET PMC-1970624 ISSUE 10
PM4351 COMET
COMBINED E1/T1 TRANSCEIVER
Pin Name
Type
Pin No. -RI -NI G3
Function
RDB
Input
23
Active Low Read Enable (RDB). RDB is pulsed low to enable a COMET register read access. The COMET drives the D[7:0] bus with the contents of the addressed register while RDB and CSB are both low.
WRB
Input
24
J2
Active Low Write Strobe (WRB). WRB is pulsed low to enable a COMET register write access. The D[7:0] bus contents are clocked into the addressed normal mode register on the rising edge of WRB while CSB is low.
ALE
Input
45
G9
Address Latch Enable (ALE). This signal latches the address bus contents, A[8:0], when low, allowing the COMET to be interfaced to a multiplexed address/data bus. When ALE is high, the address latches are transparent.
D[0] D[1] D[2] D[3] D[4] D[5] D[6] D[7] A[0] A[1] A[2] A[3] A[4] A[5] A[6] A[7] A[8] RSTB
I/O
26 27 28 29 32 33 34 35
H3 J4 H4 F4 G5 F5 H6 J7 J6 H5 H7 J8 G6 J9 H8 G7 H9 H2
Bi-directional Data Bus (D[7:0]). This bus is used during read and write accesses to internal COMET registers.
Input
36 37 38 39 40 41 42 43 44
Address bus (A[8:0]). This bus selects specific registers during COMET register accesses.
Input
22
Active Low Reset (RSTB). When forced low, RSTB will asynchronously reset the COMET. RSTB is a Schmitt-trigger input with integral pull-up. When resetting the device, RSTB must be asserted for a minimum of 100 ns to ensure that the COMET is completely reset.
INTB
OD Output
25
J3
Active Low Open-drain Interrupt (INTB). INTB drives low when an unmasked interrupt event is detected on any of the internal interrupt sources. Note that INTB will remain low until all active, unmasked interrupt sources are acknowledged at their source at which time, INTB will tristate.
PROPRIETARY AND CONFIDENTIAL
27
STANDARD PRODUCT DATA SHEET PMC-1970624 ISSUE 10
PM4351 COMET
COMBINED E1/T1 TRANSCEIVER
Table 9
Pin Name
- Power and Ground (25 pins)
Type Pin No. -RI -NI D2 E6 G4 D4 E7 J5 F2 F8 G1 F9 G8 Internal Power Pins (VDDI[2:1]). The internal power pins should be connected to a well-decoupled +3.3 V DC supply in common with VDDO. Internal Ground Pins (VSSI[2:1]). The internal ground pins should be connected to GND in common with VSSO. +5 V Bias (BIAS). The BIAS input facilitates 5 V tolerance on the inputs. BIAS must be connected to a well-decoupled +5 V rail if 5 V tolerant inputs are required. If 5 V tolerant inputs are not required, BIAS must be connected to a well-decoupled 3.3 V DC supply together with the power pins VDDO[3:1] and VDDI[3:1]. Output Ground Pins (VSSO[3:1]). The output ground pins should be connected to GND in common with VSSI. Output Power Pins (VDDO[3:1]). The output power pins should be connected to a well-decoupled +3.3 V DC supply in common with VDDI. Function
VDDO1 VDDO2 VDDO3 VSSO1 VSSO2 VSSO3 VDDI1 VDDI2 VSSI1 VSSI2 BIAS
Power
53 8 30
Ground
52 9 31
Power
48 14
Ground
47 15
Input
46
TAVD1
Analog Power
1
A1
Transmit Analog Power (TAVD1). TAVD1 provides power for the transmit LIU reference circuitry. TAVD1 should be connected to analog +3.3 V.
TAVD2 TAVD3 TAVD4
Analog Power
74 77 71
B4 B5 A5
Transmit Analog Power (TAVD2, TAVD3). TAVD2 and TAVD3 supply power for the transmit LIU output drivers. TAVD2 and TAVD3 should be connected to analog +3.3 V.
Analog Power
Transmit Analog Power (TAVD4). TAVD4 supplies power for the transmit clock synthesis unit. TAVD4 should be connected to analog +3.3 V.
TAVS1
Analog Ground
2
B2
Transmit Analog Ground (TAVS1). TAVS1 provides ground for the transmit LIU reference circuitry. TAVS1 should be connected to analog GND.
TAVS2 TAVS3 TAVS4
Analog Ground
75 78 70
A3 B3 C6
Transmit Analog Ground (TAVS2A, TAVD2B). TAVS2A and TAVS2B supply ground for the transmit LIU output drivers. TAVS2A and TAVS2B should be connected to analog GND.
Analog Ground
Transmit Analog Ground (TAVS4). TAVS supplies ground for the transmit clock synthesis unit. TAVS4 should be connected to analog GND.
RAVD1
Analog Power
61
A9
Receive Analog Power (RAVD1). RAVD1 supplies power for the receive LIU input equalizer. RAVD1 should be connected to analog +3.3 V.
RAVD2
Analog Power
65
A7
Receive Analog Power (RAVD2). RAVD2 supplies power for the receive LIU peak detect and slicer. RAVD2 should be connected to analog +3.3 V.
RAVS1
Analog Ground
62
B8
Receive Analog Ground (RAVS1). RAVS1 supplies power for the receive LIU input equalizer. RAVS1 should be connected to analog GND.
PROPRIETARY AND CONFIDENTIAL
28
STANDARD PRODUCT DATA SHEET PMC-1970624 ISSUE 10
PM4351 COMET
COMBINED E1/T1 TRANSCEIVER
Pin Name
Type
Pin No. -RI -NI B7
Function
RAVS2
Analog Ground
66
Receive Analog Ground (RAVS2). RAVS2 supplies power for the receive LIU peak detect and slicer. RAVS2 should be connected to analog GND.
QAVD
Analog Power
67
A6
Quiet Analog Power (QAVD). QAVD supplies power for the core analog circuitry. QAVD should be connected to analog +3.3 V.
QAVS
Analog Ground
69
D6
Quiet Analog Ground (QAVS). QAVS supplies ground for the core analog circuitry. QAVS should be connected to analog GND.
PROPRIETARY AND CONFIDENTIAL
29
STANDARD PRODUCT DATA SHEET PMC-1970624 ISSUE 10
PM4351 COMET
COMBINED E1/T1 TRANSCEIVER
Table 10 Function
- PM4351-RI Pin Summary Pins 4 pins 4 pins 6 pins 4 pins 5 pins 4 pins 5 pins 23 pins 25 pins 80 pins 80 pins PM4351-NI Pin Summary Pins 4 pins 4 pins 6 pins 4 pins 5 pins 4 pins 5 pins 23 pins 25 pins 80 pins 1 pin 81 pins
Backplane Transmit Interface Backplane Receive Interface Transmit Line Interface Receive Line Interface Timing Options Control Analog Support Circuitry JTAG (IEEE 1149.1) Boundary Scan Test Interface Microprocessor Interface Power and Ground Total Functions Pins Total Table 11 Function Backplane Transmit Interface Backplane Receive Interface Transmit Line Interface Receive Line Interface Timing Options Control Analog Support Circuitry JTAG (IEEE 1149.1) Boundary Scan Test Interface Microprocessor Interface Power and Ground Total Functions Pins Unused Pins Total Notes on Pin Description:
PROPRIETARY AND CONFIDENTIAL
30
STANDARD PRODUCT DATA SHEET PMC-1970624 ISSUE 10
PM4351 COMET
COMBINED E1/T1 TRANSCEIVER
1. All COMET digital inputs and bi-directional pins present minimum capacitive loading and operate at TTL logic levels. 2. All COMET digital outputs and bi-directional pins have at least 2 mA drive capability. The BTCLK and BRCLK outputs, have 6 mA drive capability. The transmit analog outputs (TXTIP and TXRING) have built-in short circuit current limiting. 3. Inputs RSTB, TMS, TDI and TRSTB have internal pull-up resistors. 4. The VSSI and VSSO ground pins are not internally connected together. Failure to connect these pins externally may cause malfunction or damage the COMET. 5. The VDDI and VDDO power pins are not internally connected together. Failure to connect these pins externally may cause malfunction or damage the COMET. 6. The recommended power supply sequencing is as follows: a) During power-up, the voltage on the BIAS pin must be kept equal to or greater than the voltage on the VDDO3, VDDO2, VDDO1, VDDI2 and VDDI1 pins, to avoid damage to the device. b) VDDI power must be supplied either before VDDO or simultaneously with VDDO. Connection of VDDI and VDDO to a common VDD power plane is recommended. c) The VDDI power must be applied before input pins are driven or the input current per pin be limited to less than the maximum DC input current specification (20 mA). d) Analog power supplies (TAVD1, TAVD2, TAVD3, TAVD4, RAVD1, RAVD2, QAVD) must be applied after both VDDI and VDDO have been applied or they must be current limited to the maximum latch-up current specification (100 mA). In operation, the differential voltage measured between AVD supplies and VDDI must be less than 0.5 V. The relative power sequencing of the multiple AVD power supplies is not important. e) Power down the device in the reverse sequence.
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COMBINED E1/T1 TRANSCEIVER
9 9.1
FUNCTIONAL DESCRIPTION Receive Interface Two basic receive options are available: the receive stream is presented as a TTL-compatible unipolar signal with an associated clock, or the receive data is reconstructed from unequalized pulses from a center tapped signal transformer. See Figure 5 for the recommended external analog circuitry. When the digital receive interface is enabled, the RDAT signal is expected to carry a decoded serial bit stream. RDAT can be sampled on either the rising or falling RCLKI edge. The polarity of RDAT can also be inverted. The analog receive interface is configurable to operate in both E1 and T1 shorthaul and long-haul applications. Short-haul T1 is defined as transmission over less than 655 ft of cable. Short-haul E1 is defined as transmission on any cable that attenuates the signal by less than 6 dB. For long-haul signals, unequalized long- or short-haul bipolar alternate mark inversion (AMI) signals are received as the differential voltage between the RXTIP and RXRING inputs. For short-haul, the slicing threshold is set to a fraction of the input signal's peak amplitude, and adapts to changes in this amplitude. The slicing threshold is 67% and 50% for DSX-1 and E1 applications, respectively. Abnormally low input signals are detected when the input level is below 140 mV for E1 and 105 mV for T1.
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PM4351 COMET
COMBINED E1/T1 TRANSCEIVER
Figure 5
- External Analog Interface Circuits
TXT IP 1 TXT IP 2
TV RE F
TXR IN G 1 TXR IN G 2
AT B
RXT IP
RXR IN G
TXT IP 1 TXT IP 2
TV RE F
TXR IN G 1 TXR IN G 2
AT B
RXT IP
RXR IN G
Figure 5 gives the recommended external protection circuitry for two cases:
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PM4351 COMET
COMBINED E1/T1 TRANSCEIVER
1) for systems requiring phantom feed or inter-building line protection 2) for systems with no DC current requirements or intra-building line protection. See Table 12 for the descriptions of components for Figure 5. See Table 14 for the descriptions of values for the transformer turns ratio, n, Rt1 and Rt2 for Figure 5. Figure 5 assumes primary protectors (like carbon blocks) are also present. The protection resistors (PTCs) of 1 (but can be up to about 2) are optional, but if not included then 1 to 2 resistor with a series fuse should be used instead. Note that the crowbar devices (Z1 - Z4) are not required if the transformer's isolation rating is not exceeded. Table 12 - External Component Descriptions Description Typically 12.7=1% Resistors (see Table 14) 18.2=1% Resistor for T1 & 120 E1 13=1% Resistor for 75= E1 (assuming a 1:2.42 transformer) 4.7F10% Capacitors TC250-180 LC01-6 LC03-6 SRDA3.3-4 SGT27B13 50436 (single) T1137 (dual) TG23-1505NS (single) TG23-1505N1 (dual) Raychem Semtech Semtech Semtech Harris Midcom Pulse Halo Halo Part # Source
Component Rt1 & Rt2 Rterm
C0 & C1
PTC1 - PTC4 1 Positive Temperature Coefficient R TVS1 & TVS2 6V Bi-directional Transient Voltage Suppressor Diode TVS2 & TVS3 6V Bi-directional Transient Voltage Suppressor Diode D1 Z1 - Z4 T1 & T2 Surge Protector Diode Array Bi-directional Transient Surge Suppressors Generally 1:2.42CT Transformers (see Table 14)
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PM4351 COMET
COMBINED E1/T1 TRANSCEIVER
T3 & T4
Generally 1:2.42CT Transformers with centre taps floating (see Table 14)
50436 (single) T1137 (dual) TG23-1505NS (single) TG23-1505N1 (dual)
Midcom Pulse Halo Halo
Table 13 Case
- Typical Input Return Loss at Receiver n 1:2.42 1:2.42 1:2.42 Rterm 18.2=1% 18.2=1% 13.0=1% Typical IRL 30.2dB 24.4dB 43.3dB
T1: Zo=100 E1: Zo=120 E1: Zo=75
Table 14 Case
- Termination Resistors, Transformer Ratios and TRL n 1:2.42 1:2.42 1:2.42 1:2.42 1:2.421 1:2.42 1:2.42 1:2.42 1:2.42 12.7=1% 12.7=1% 8.06=1% 12.7=1% 12.7=1% 12.7=1% 12.7=1% 12.7=1% 12.7=1% 8.06=1% 12.7=1% 12.7=1% 12.7=1% 12.7=1% Rt1 12.7=1% Rt2 12.7=1% Typical TRL 14.1dB 0dB 19.4dB 9.6dB 18.8dB 14.1dB 14.1dB 14.1dB 14.1dB
SH T1: Zo=100 SH T1: Zo=100 SH E1: Zo=120 SH E1: Zo=75 SH E1: Zo=751 LH T1 LBO=0dB:= Zo=100 LH T1 LBO=-7.5dB: Zo=100 LH T1 LBO=-15dB: Zo=100 LH T1 LBO=-22.5dB:= Zo=100
Notes: 1) Headroom power is about 30% higher in this case. 9.2 Clock and Data Recovery (CDRC) The Clock and Data Recovery function is provided by the Clock and Data Recovery (CDRC) block. The CDRC provides clock and PCM data recovery,
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PM4351 COMET
COMBINED E1/T1 TRANSCEIVER
B8ZS and HDB3 decoding, line code violation detection, and loss of signal detection. It recovers the clock from the incoming RZ data pulses using a digital phase-locked-loop and reconstructs the NRZ data. Loss of signal is indicated after a programmable threshold of consecutive bit periods of the absence of pulses on both the positive and negative line pulse inputs and is cleared after the occurrence of a single line pulse. An alternate loss of signal indication is provided which is cleared upon meeting an 1-in-8 pulse density criteria for T1 and a 1-in-4 pulse density criteria for E1. If enabled, a microprocessor interrupt is generated when a loss of signal is detected and when the signal returns. A line code violation is defined as a bipolar violation (BPV) for AMI-coded signals, is defined as a BPV that is not part of a zero substitution code for B8ZS-coded signals, and is defined as a bipolar violation of the same polarity as the last bipolar violation for HDB3-coded signals. In T1 mode, the input jitter tolerance of the COMET complies with the Bellcore Document TA-TSY-000170 and with the AT&T specification TR62411, as shown in Figure 6. The tolerance is measured with a QRSS sequence (220-1 with 14 zero restriction). The CDRC block provides two algorithms for clock recovery that result in differing jitter tolerance characteristics. The first algorithm (when the ALGSEL register bit is logic 0) provides good low frequency jitter tolerance, but the high frequency tolerance is close to the TR62411 limit. The second algorithm (when ALGSEL is logic 1) provides much better high frequency jitter tolerance at the expense of the low frequency tolerance; the low frequency tolerance of the second algorithm is approximately 80% that of the first algorithm.
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PM4351 COMET
COMBINED E1/T1 TRANSCEIVER
Figure 6
- T1 Jitter Tolerance
ALGSEL=1 at 772 kHz with 36 dB of attenuation
10 ALGSEL=0 at 772 kHz with 36 dB of attenuation Sine Wave Jitter Amplitude P. to P. (UI) Log Scale 1.0
Acceptable Range
0.3 0.2
Bellcore Spec. AT&T Spec.
0.1 0.1 0.30 0.31 1.0 10 100 Sine Wave Jitter Frequency (kHz) Log Scale
For E1 applications, the input jitter tolerance complies with the ITU-T Recommendation G.823 "The Control of Jitter and Wander Within Digital Networks Which are Based on the 2048 kbit/s Hierarchy." Figure 7 illustrates this specification and the performance of the phase-locked loop when the ALGSEL register bit is logic 0.
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PM4351 COMET
COMBINED E1/T1 TRANSCEIVER
Figure 7
- Compliance with ITU-T Specification G.823 for E1 Input Jitter
10
SINEWAVE JITTER AMPLITUDE P. TO P. (UI) LOG SCALE
DPLL TOLERANCE WITH AMI ENCODED 15 2 -1 PRBS
IN SPEC REGION
DPLL TOLERANCE WITH HDB3 ENCODED 15 2 -1 PRBS
1.5 1
REC. G823 JITTER TOLERANCE SPECIFICATION
0.2
0.1 10 3
2.4 10
4
1.8 10
5
SINEWAVE JITTER FREQUENCY, Hz - LOG SCALE
9.3
T1 Framer
The T1 framing function is provided by the T1-FRMR block. This block searches for the framing bit position of SF, ESF, J1, T1DM or SLC(R)96 framing formats in the incoming recovered PCM stream. When searching for frame, the T1-FRMR examines each of the 193 (SF, T1DM or SLC(R)96) or each of 4*193 (ESF or J1) framing bit candidates concurrently. The time required to find frame alignment to an error-free PCM stream containing randomly distributed channel data (i.e. each bit in the channel data has a 50% probability of being 1 or 0) is dependent upon the framing format. For standard superframe format (SF, also known as D4 format), the T1-FRMR block
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COMBINED E1/T1 TRANSCEIVER
will determine frame alignment within 4.4 ms 99 times out of 100. For SLC(R)96 format, the T1-FRMR will determine frame alignment within 9.9 ms 99 times out of 100. For extended superframe format (ESF) and J1, the T1-FRMR will determine frame alignment within 15 ms 99 times out of 100. For T1DM format, the T1-FRMR will determine frame alignment within 1.125 ms 99 times out of 100. Once the T1-FRMR has found frame, the incoming PCM data is continuously monitored for framing bit errors, bit error events (a framing bit error in SF or SLC(R)96, a framing bit error or sync bit error in T1DM, or a CRC-6 error in ESF and J1), and severe errored framing events. The T1-FRMR also detects loss of frame, based on a selectable ratio of framing bit errors. The T1-FRMR extracts the Yellow alarm signal bits from the incoming PCM data stream in SF and SLC(R)96 framing formats, and extracts the Y-bit from the T1DM sync word in T1DM framing format. The T1-FRMR also extracts the SLC(R)96 data link in SLC(R)96 framing format (with external logic), extracts the facility data link bits in the ESF and J1 framing formats, and extracts the R-bit from the T1DM sync word in T1DM framing format. The T1-FRMR can also be disabled to allow reception of unframed data.
9.4 E1 Framer
The E1 framing function is provided by the E1-FRMR block. The E1-FRMR block searches for basic frame alignment, CRC multiframe alignment, and channel associated signaling (CAS) multiframe alignment in the incoming recovered PCM stream. Once the E1-FRMR has found basic (or FAS) frame alignment, the incoming PCM data stream is continuously monitored for FAS/NFAS framing bit errors. Framing bit errors are accumulated in the framing bit error counter contained in the PMON block. Once the E1-FRMR has found CRC multiframe alignment, the PCM data stream is continuously monitored for CRC multiframe alignment pattern errors, and CRC-4 errors. CRC-4 errors are accumulated in the CRC error counter of the PMON block. Once the E1-FRMR has found CAS multiframe alignment, the PCM data is continuously monitored for CAS multiframe alignment pattern errors. The E1-FRMR also detects and indicates loss of basic frame, loss of CRC multiframe, and loss of CAS multiframe, based on user-selectable criteria. The reframe operation can be initiated by software (via the E1-FRMR Frame Alignment Options Register), by excessive CRC errors, or when CRC multiframe alignment is not found within 400 ms. The E1-FRMR also identifies the position of the frame, the CAS multiframe, and the CRC multiframe.
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COMBINED E1/T1 TRANSCEIVER
The E1-FRMR extracts the contents of the International bits (from both the FAS frames and the NFAS frames), the National bits, and the Extra bits (from timeslot 16 of frame 0 of the CAS multiframe), and stores them in the E1-FRMR International/National Bits register and the E1-FRMR Extra Bits register. Moreover, the FRMR also extracts submultiframe-aligned 4-bit codewords from each of the National bit positions Sa4 to Sa8, and stores them in microprocessor-accessible registers that are updated every CRC submultiframe. The E1-FRMR identifies the raw bit values for the Remote (or distant frame) Alarm (bit 3 in timeslot 0 of NFAS frames) and the Remote Signaling Multiframe (or distant multiframe) Alarm (bit 6 of timeslot 16 of frame 0 of the CAS multiframe) via the E1-FRMR International/National Bits Register, and the E1-FRMR Extra Bits Register respectively. Access is also provided to the "debounced" remote alarm and remote signaling multiframe alarm bits which are set when the corresponding signals have been a logic 1 for 2 or 3 consecutive occurrences, as per Recommendation O.162. Detection of AIS and timeslot 16 AIS are provided. AIS is also integrated, and an AIS Alarm is indicated if the AIS condition has persisted for at least 100 ms. The out of frame (OOF=1) condition is also integrated, indicating a Red Alarm if the OOF condition has persisted for at least 100 ms. An interrupt may be generated to signal a change in the state of any status bits (OOF, OOSMF, OOCMF, AIS or RED), and to signal when any event (RAI, RMAI, AISD, COFA, FER, SMFER, CMFER, CRCE or FEBE) has occurred. Additionally, interrupts may be generated every frame, CRC submultiframe, CRC multiframe or signaling multiframe.
Basic Frame Alignment Procedure
The E1-FRMR searches for basic frame alignment using the algorithm defined in ITU-T Recommendation G.706 sections 4.1.2 and 4.2. The algorithm finds frame alignment by using the following sequence: 1. Search for the presence of the correct 7-bit FAS (`0011011'); 2. Check that the FAS is absent in the following frame by verifying that bit 2 of the assumed non-frame alignment sequence (NFAS) TS 0 byte is a logic 1; 3. Check that the correct 7-bit FAS is present in the assumed TS 0 byte of the next frame. If either of the conditions in steps 2 or 3 are not met, a new search for frame alignment is initiated in the bit immediately following the second 7-bit FAS sequence check. This "hold-off" is done to ensure that new frame alignment
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COMBINED E1/T1 TRANSCEIVER
searches are done in the next bit position, modulo 512. This facilitates the discovery of the correct frame alignment, even in the presence of fixed timeslot data imitating the FAS. These algorithms provide robust framing operation even in the presence of random bit errors: framing with algorithm #1 or #2 provides a 99.98% probability of finding frame alignment within 1 ms in the presence of 10-3 bit error rate and no mimic patterns. Once frame alignment is found, the block sets the OOF indication low, indicates a change of frame alignment (if it occurred), and monitors the frame alignment signal, indicating errors occurring in the 7-bit FAS pattern and in bit 2 of NFAS frames, and indicating the debounced value of the Remote Alarm bit (bit 3 of NFAS frames). Using debounce, the Remote Alarm bit has <0.00001% probability of being falsely indicated in the presence of a 10-3 bit error rate. The block declares loss of frame alignment if 3 consecutive FASs have been received in error or, additionally, if bit 2 of NFAS frames has been in error for 3 consecutive occasions. In the presence of a random 10-3 bit error rate the frame loss criteria provides a mean time to falsely lose frame alignment of >12 minutes. The E1-FRMR can be forced to initiate a basic frame search at any time when any of the following conditions are met:
* * *
the software re-frame bit in the E1-FRMR Frame Alignment Options register goes to logic 1; the CRC Frame Find Block is unable to find CRC multiframe alignment; or the CRC Frame Find Block accumulates excessive CRC evaluation errors ( 915 CRC errors in 1 second) and is enabled to force a re-frame under that condition.
CRC Multiframe Alignment Procedure
The E1-FRMR searches for CRC multiframe alignment by observing whether the International bits (bit 1 of TS 0) of NFAS frames follow the CRC multiframe alignment pattern. Multiframe alignment is declared if at least two valid CRC multiframe alignment signals are observed within 8 ms, with the time separating two alignment signals being a multiple of 2 ms Once CRC multiframe alignment is found, the OOCMFV register bit is set to logic 0, and the E1-FRMR monitors the multiframe alignment signal, indicating errors occurring in the 6-bit MFAS pattern, errors occurring in the received CRC and the value of the FEBE bits (bit 1 of frames 13 and 15 of the multiframe). The E1-FRMR declares loss of CRC multiframe alignment if basic frame
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COMBINED E1/T1 TRANSCEIVER
alignment is lost. However, once CRC multiframe alignment is found, it cannot be lost due to errors in the 6-bit MFAS pattern. Under the CRC-to-non-CRC interworking algorithm, if the E1-FRMR can achieve basic frame alignment with respect to the incoming PCM data stream, but is unable to achieve CRC-4 multiframe alignment within the subsequent 400 ms, the distant end is assumed is assumed to be a non CRC-4 interface. The details of this algorithm are illustrated in the state diagram in Figure 8.
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COMBINED E1/T1 TRANSCEIVER
Figure 8
- CRC Multiframe Alignment Algorithm
O ut of Fram e
3 consecutiv e FAS or NF AS errors; m anual refram e; or excessiv e C RC errors
FAS_Find_1
NFAS not found next fram e
FAS_Find_1_Par
FAS found NFAS not found next fram e
FAS found
NFAS_Find
NFAS found next fram e FAS not found next fram e
NFAS_Find_Par
NFAS found next fram e FAS not found next fram e
FAS_Find_2
FAS found next fram e 8m s expire
Start 400m s tim er and 8m s tim er
FAS_Find_2_Par
FAS found next fram e
Start 8m s tim er
BFA
CRC MFA
8m s expire and NOT(400m s expire)
Reset BF A to m ost recently found alignm ent
BFA_Par
400m s expire
CRCMFA_Par
CRC to CRC Interworking
CR CMFA_Par (Optional setting)
CRC to non-CRC Interworking
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COMBINED E1/T1 TRANSCEIVER
Table 15 State
- E1-FRMR Framing States Out of Frame Out of Offline Frame
FAS_Find_1 NFAS_Find FAS_Find_2 BFA CRC to CRC Interworking FAS_Find_1_Par NFAS_Find_Par FAS_Find_2_Par BFA_Par CRC to non-CRC Interworking
Yes Yes Yes No No No No No No No
No No No No No Yes Yes Yes No No
The states of the primary basic framer and the parallel/offline framer in the E1-FRMR block at each stage of the CRC multiframe alignment algorithm are shown in Table 15. From an out of frame state, the E1-FRMR attempts to find basic frame alignment in accordance with the FAS/NFAS/FAS G.706 Basic Frame Alignment procedure outlined above. Upon achieving basic frame alignment, a 400 ms timer is started, as well as an 8 ms timer. If two CRC multiframe alignment signals separated by a multiple of 2 ms are observed before the 8 ms timer has expired, CRC multiframe alignment is declared. If the 8 ms timer expires without achieving multiframe alignment, a new offline search for basic frame alignment is initiated. This search is performed in accordance with the Basic Frame Alignment procedure outlined above. However, this search does not immediately change the actual basic frame alignment of the system (i.e., PCM data continues to be processed in accordance with the first basic frame alignment found after an out of frame state while this frame alignment search occurs as a parallel operation). When a new basic frame alignment is found by this offline search, the 8 ms timer is restarted. If two CRC multiframe alignment signals separated by a multiple of 2 ms are observed before the 8 ms timer has expired, CRC multiframe alignment
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COMBINED E1/T1 TRANSCEIVER
is declared and the basic frame alignment is set accordingly (i.e., the basic frame alignment is set to correspond to the frame alignment found by the parallel offline search, which is also the basic frame alignment corresponding to the newly found CRC multiframe alignment). Subsequent expirations of the 8 ms timer will likewise reinitiate a new search for basic frame alignment. If, however, the 400 ms timer expires at any time during this procedure, the E1-FRMR stops searching for CRC multiframe alignment and declares CRC-to-non-CRC interworking. In this mode, the E1-FRMR may be optionally set to either halt searching for CRC multiframe altogether, or may continue searching for CRC multiframe alignment using the established basic frame alignment. In either case, no further adjustments are made to the basic frame alignment, and no offline searches for basic frame alignment occur once CRC-to-non-CRC interworking is declared: it is assumed that the established basic frame alignment at this point is correct.
AIS Detection
When an unframed all-ones receive data stream is received, an AIS defect is indicated by setting the AISD bit to logic 1 when fewer than three zero bits are received in 512 consecutive bits or, optionally, in each of two consecutive periods of 512 bits. The AISD bit is reset to logic 0 when three or more zeros in 512 consecutive bits or in each of two consecutive periods of 512 bits. Finding frame alignment will also cause the AISD bit to be set to logic 0.
Signaling Frame Alignment
Once the basic frame alignment has been found, the E1-FRMR searches for Channel Associated Signaling (CAS) multiframe alignment using the following G.732 compliant algorithm: signaling multiframe alignment is declared when at least one non-zero time slot 16 bit is observed to precede a time slot 16 containing the correct CAS alignment pattern, namely four zeros ("0000") in the first four bit positions of timeslot 16. Once signaling multiframe alignment has been found, the E1-FRMR sets the OOSMFV bit of the E1-FRMR Framing Status register to logic 0, and monitors the signaling multiframe alignment signal, indicating errors occurring in the 4-bit pattern, and indicating the debounced value of the Remote Signaling Multiframe Alarm bit (bit 6 of timeslot 16 of frame 0 of the multiframe). Using debounce, the Remote Signaling Multiframe Alarm bit has < 0.00001% probability of being falsely indicated in the presence of a 10-3 bit error rate. The block declares loss of CAS multiframe alignment if two consecutive CAS multiframe alignment signals have been received in error, or additionally, if all the bits in time slot 16 are logic 0 for 1 or 2 (selectable) CAS multiframes. Loss of
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CAS multiframe alignment is also declared if basic frame alignment has been lost.
National Bit Extraction
The E1-FRMR extracts and assembles the submultiframe-aligned National bit codewords Sa4[1:4] , Sa5[1:4] , Sa6[1:4] , Sa7[1:4] and Sa8[1:4]. The corresponding register values are updated upon generation of the CRC submultiframe interrupt. This E1-FRMR also detects the V5.2 link ID signal, which is defined as the condition where 2 out of 3 Sa7 bits are zeroes. Upon reception of this Link ID signal, the V52LINKV bit of the E1-FRMR Framing Status register is set to logic 1. This bit is cleared to logic 0 when 2 out of 3 Sa7 bits are ones.
Alarm Integration
The OOF and the AIS defects are integrated, verifying that each condition has persisted for 104 ms ( 6 ms) before indicating the alarm condition. The alarm is removed when the condition has been absent for 104 ms ( 6 ms). The AIS alarm algorithm accumulates the occurrences of AISD (AIS detection). The E1-FRMR counts the occurrences of AISD over a 4 ms interval and indicates a valid AIS is present when 13 or more AISD indications (of a possible 16) have been received. Each interval with a valid AIS presence indication increments an interval counter which declares AIS Alarm when 25 valid intervals have been accumulated. An interval with no valid AIS presence indication decrements the interval counter. The AIS Alarm declaration is removed when the counter reaches 0. This algorithm provides a 99.8% probability of declaring an AIS Alarm within 104 ms in the presence of a 10-3 mean bit error rate. The Red alarm algorithm monitors occurrences of OOF over a 4 ms interval, indicating a valid OOF interval when one or more OOF indications occurred during the interval, and indicating a valid in frame (INF) interval when no OOF indication occurred for the entire interval. Each interval with a valid OOF indication increments an interval counter which declares Red Alarm when 25 valid intervals have been accumulated. An interval with valid INF indication decrements the interval counter; the Red Alarm declaration is removed when the counter reaches 0. This algorithm biases OOF occurrences, leading to declaration of Red alarm when intermittent loss of frame alignment occurs.
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9.5
T1 Inband Loopback Code Detector (IBCD)
The T1 Inband Loopback Code Detection function is provided by the IBCD block. This block detects the presence of either of two programmable INBAND LOOPBACK ACTIVATE and DEACTIVATE code sequences in either framed or unframed data streams. Each INBAND LOOPBACK code sequence is defined as the repetition of the programmed code in the PCM stream for at least 5.1 seconds. The code sequence detection and timing is compatible with the specifications defined in T1.403-1993, TA-TSY-000312, and TR-TSY-000303. LOOPBACK ACTIVATE and DEACTIVATE code indication is provided through internal register bits. An interrupt is generated to indicate when either code status has changed.
9.6 T1 Pulse Density Violation Detector (PDVD)
The Pulse Density Violation Detection function is provided by the PDVD block. The block detects pulse density violations of the requirement that there be N ones in each and every time window of 8(N+1) data bits (where N can equal 1 through 23). The PDVD also detects periods of 16 consecutive zeros in the incoming data. Pulse density violation detection is provided through an internal register bit. An interrupt is generated to signal a 16 consecutive zero event, and/or a change of state on the pulse density violation indication. The PDVD block is available when the analog RXTIP and RXRING inputs are enabled (i.e., when the RUNI bit in the Receive Line Interface Configuration register is logic 0).
9.7 Performance Monitor Counters (PMON)
The Performance Monitor Counters function is provided by the PMON block. The block accumulates CRC error events, Frame Synchronization bit error events, Line Code Violation events, and Out Of Frame events, or optionally, Change of Frame Alignment (COFA) events with saturating counters over consecutive intervals as defined by the period of the supplied transfer clock signal (typically 1 second). When the transfer clock signal is applied, the PMON transfers the counter values into holding registers and resets the counters to begin accumulating events for the interval. The counters are reset in such a manner that error events occurring during the reset are not missed. If the holding registers are not read between successive transfer clocks, an OVERRUN register bit is asserted. For T1, a line code violation is either a bipolar violation (only those not part of a zero substitution code for B8ZS-coded and HDB3 signals) or excessive zeros. Excessive zeros is a sequence of zeros greater than 15 bits long for an AMI-code
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COMBINED E1/T1 TRANSCEIVER
signal and greater than 7 bits long for a B8ZS-coded signals. The inclusion of excessive zeros in the line code violation count can be disabled. For E1, a line code violation is defined as a bipolar violation (BPV) for AMI-coded signals and is defined as a bipolar violation of the same polarity as the last bipolar violation for HDB3-coded signals. Generation of the transfer clock within the COMET chip is performed by writing to any counter register location or by writing to the Global PMON Update register. The holding register addresses are contiguous to facilitate faster polling operations.
9.8 T1 Bit Oriented Code Detector (RBOC)
The Bit Oriented Code detection function is provided by the RBOC block. This block detects the presence of 63 of the possible 64 bit oriented codes transmitted in the Facility Data Link channel in ESF framing format, as defined in ANSI T1.403-1993 and in TR-TSY-000194. The 64th code (111111) is similar to the DL FLAG sequence and is used by the RBOC to indicate no valid code received. Bit oriented codes are received on the Facility Data Link channel as a 16-bit sequence consisting of 8 ones, a zero, 6 code bits, and a trailing zero (111111110xxxxxx0) which is repeated at least 10 times. The RBOC can be enabled to declare a received code valid if it has been observed for 8 out of 10 times or for 4 out of 5 times, as specified by the AVC bit in the control register. Valid BOC are indicated through an internal status register. The BOC bits are set to all ones (111111) if no valid code has been detected. An interrupt is generated to signal when a detected code has been validated, or optionally, when a valid code goes away (i.e. the BOC bits go to all ones).
9.9 HDLC Receiver (RDLC)
The HDLC Receiver function is provided by the RDLC block. The RDLC is a microprocessor peripheral used to receive HDLC frames. Three RDLC blocks are provided for flexible extraction of standardized data links:
* * * *
T1 ESF facility data link T1DM data link ISDN D-channel E1 Common Channel Signaling data link
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* *
V5.1/V5.2 D-channel and C-channels. E1 Sa-bit data link
The RDLC detects the change from flag characters to the first byte of data, removes stuffed zeros on the incoming data stream, receives packet data, and calculates the CRC-CCITT frame check sequence (FCS). In the address matching mode, only those packets whose first data byte matches one of two programmable bytes or the universal address (all ones) are stored in the FIFO. The two least significant bits of the address comparison can be masked for LAPD SAPI matching. Received data is placed into a 128-byte FIFO buffer. An interrupt is generated when a programmable number of bytes are stored in the FIFO buffer. Other sources of interrupt are detection of the terminating flag sequence, abort sequence, or FIFO buffer overrun. The Status Register contains bits which indicate the overrun or empty FIFO status, the interrupt status, and the occurrence of first flag or end of message bytes written into the FIFO. The Status Register also indicates the abort, flag, and end of message status of the data just read from the FIFO. On end of message, the Status Register indicates the FCS status and if the packet contained a non-integer number of bytes.
9.10 T1 Alarm Integrator (ALMI)
The T1 Alarm Integration function is provided by the ALMI block. This block detects the presence of Yellow, Red, and AIS Carrier Fail Alarms (CFA) in SF, T1DM, SLC(R)96, or ESF formats. The alarm detection and integration is compatible with the specifications defined in Bell Pub 43801, TA-TSY-000278, TR-TSY-000008, ANSI T1.403-1993, and TR-TSY-000191. Alarm detection and validation for SLC(R)96 is handled the same as SF framing format. The ALMI block declares the presence of Yellow alarm when the Yellow pattern has been received for 425 ms ( 50 ms); the Yellow alarm is removed when the Yellow pattern has been absent for 425 ms ( 50 ms). The presence of Red alarm is declared when an out-of-frame condition has been present for 2.55 sec ( 40 ms); the Red alarm is removed when the out-of-frame condition has been absent for 16.6 sec ( 500 ms). In T1DM framing format the Red alarm declaration criteria can be selected to be either 400 ms ( 100 ms) or 2.55 sec ( 40 ms); removal of the Red alarm in T1DM can be selected to be either 100 ms ( 50 ms) or 16.6 sec ( 500 ms). The presence of AIS alarm is declared when an out-of-frame condition and all-ones in the PCM data stream
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have been present for 1.5 sec ( 100 ms); the AIS alarm is removed when the AIS condition has been absent for 16.8 sec ( 500 ms). CFA alarm detection algorithms operate in the presence of a random 10-3 bit error rate. The ALMI also indicates the presence or absence of the Yellow, Red, and AIS alarm signal conditions over 40 ms , 40 ms and 60 ms intervals, respectively, allowing an external microprocessor to integrate the alarm conditions via software with any user-specific algorithms. Alarm indication is provided through internal register bits.
9.11 Receive Elastic Store (RX-ELST)
The Receive Elastic Store (RX-ELST) synchronizes incoming PCM frames to the local backplane clock, BRCLK. The frame data is buffered in a two-frame circular data buffer. Input data is written to the buffer using a write pointer and output data is read from the buffer using a read pointer. When the elastic store is being used, if the average frequency of the incoming data is greater than the average frequency of the backplane clock, the write pointer will catch up to the read pointer and the buffer will be filled. Under this condition a controlled slip will occur when the read pointer crosses the next frame boundary. The following frame of PCM data will be deleted. If the average frequency of the incoming data is less than the average frequency of the backplane clock, the read pointer will catch up to the write pointer and the buffer will be empty. Under this condition a controlled slip will occur when the read pointer crosses the next frame boundary. The last frame which was read will be repeated. A slip operation is always performed on a frame boundary. When the backplane timing is derived from the receive line data (i.e. BRCLK is an output), the elastic store can be bypassed to eliminate the two frame delay. In this configuration the elastic store can be used to measure frequency differences between the recovered line clock and another 1.544 MHz or 2.048 MHz clock applied to the BRCLK input. A typical example might be to measure the difference in frequency between two received streams (i.e. EastWest frequency difference) by monitoring the number of SLIP occurrences of one direction with respect to the other. To allow for the extraction of signaling information in the PCM data channels, superframe identification is also passed through the RX-ELST.
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For payload conditioning, the RX-ELST may optionally insert a programmable idle code into all channels when the framer is out of frame synchronization. This code is set to all 1's when the RX-ELST is reset.
9.12 Receive Jitter Attenuator (RJAT)
The Receive Jitter Attenuator (RJAT) digital PLL attenuates the jitter present on the RXTIP/RXRING or RDAT inputs. The attenuation is only performed when the RJATBYP register bit is a logic 0. The jitter characteristics of the Receive Jitter Attenuator (RJAT) are the same as the Transmit Jitter Attenuator (TJAT).
9.13 Signaling Extractor (SIGX)
The Signaling Extraction (SIGX) block provides channel associated signaling (CAS) extraction from an E1 signaling multiframe or from SF and ESF T1 formats. With external logic the Signaling Extraction (SIGX) block extracts the nine bit signaling format from SLC(R)96 T1 formats. The SIGX block provides signaling bit extraction from the received data stream for T1 ESF, SF, SLC(R)96 and E1 framing formats. It selectively debounces the bits, and serializes the results onto the BRSIG output. Debouncing is performed on individual signaling bits. This BRSIG output is channel aligned with BRPCM output, and the signaling bits are repeated for the entire superframe, allowing downstream logic to reinsert signaling into any frame, as determined by system timing. The signaling data stream contains the A,B,C,D bits in the lower 4 channel bit locations (bits 5, 6, 7 and 8) in T1 ESF and E1 framing formats; in SF and SLC(R)96 formats the A and B bits are repeated in locations C and D (i.e. the signaling stream contains the bits ABAB for each channel). The SIGX block contains three superframes worth of signal buffering to ensure that there is a greater than 95% probability that the signaling bits are frozen in the correct state for a 50% ones density out-of-frame condition, as specified in TR-TSY-000170 and BELL PUB 43801. With signaling debounce enabled, the per-channel signaling state must be in the same state for 2 superframes before appearing on the serial output stream. The SIGX block provides one superframe or signaling-multiframe of signal freezing on the occurrence of slips. When a slip event occurs, the SIGX freezes the output signaling for the entire superframe in which the slip occurred; the signaling is unfrozen when the next slip-free superframe occurs. The SIGX also provides control over timeslot signaling bit fixing, data inversion and signaling debounce on a per-timeslot basis.
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The SIGX block also provides an interrupt to indicate a change of signaling state on a per channel basis.
9.14 Receive Per-channel Serial Controller (RPSC)
The Receive Per-channel Serial Controller (RPSC) function is provided by a PCSC block. The RPSC allows data and signaling trunk conditioning to be applied independently on the receive stream on a per-channel basis.
9.15 T1 Signaling Aligner (SIGA)
The T1 Signaling Aligner can be positioned before the T1 basic transmitter to provide superframe alignment of the signaling bits between the backplane and the transmit DS-1 stream. The signaling alignment block maintains signaling bit integrity across superframe boundaries.
9.16 T1 Basic Transmitter (XBAS)
The T1 Basic Transmitter (XBAS) block generates the 1.544 Mbit/s T1 data stream according to SF, ESF, T1DM or SLC(R)96 formats. In concert with the Transmit Per-Channel Serial Controller (TPSC), the XBAS block provides per channel control of idle code substitution, data inversion (either all 8 bits, sign bit only or magnitude only), digital milliwatt substitution, and zero code suppression. Three types of zero code suppression (GTE, Bell and DDS) are supported and selected on a per channel basis to provide minimum ones density control. Robbed bit signaling control and selection of the signaling source are also performed on a per-channel basis. All channels can be forced into a trunk conditioning state (idle code substitution and signaling conditioning) by use of the Master Trunk Conditioning bit in the T1 XBAS Configuration Register. A data link is provided for ESF, T1DM and SLC(R)96 modes. The data link sources include bit oriented codes and HDLC messages. Support is provided for the transmission of framed or unframed Inband Code sequences and transmission of AIS or Yellow alarm signals for all formats. PCM output signals may be selected to conform to B8ZS or AMI line coding. The transmitter can be disabled for framing via the FDIS bit in the Transmit Framing and Bypass Options register. When transmitting ESF formatted data, the framing bit, datalink bit, or the CRC-6 bit from the input PCM stream can be by-passed to the output PCM stream.
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9.17
E1 Transmitter (E1-TRAN)
The E1 Transmitter (E1-TRAN) generates a 2048 kbit/s data stream according to ITU-T recommendations, providing individual enables for frame generation, CRC multiframe generation, and channel associated signaling (CAS) multiframe generation. In concert with Transmit Per-Channel Serial Controller (TPSC), the E1-TRAN block provides per-timeslot control of idle code substitution, data inversion, digital milliwatt substitution, selection of the signaling source and CAS data. All timeslots can be forced into a trunk conditioning state (idle code substitution and signaling substitution) by use of the master trunk conditioning bit in the Configuration Register. Common Channel Signaling (CCS) is supported in time slot 16 either through the internal HDLC Transmitter (TDPR) and the Transmit Channel Insertion (TXCI) block. Support is provided for the transmission of AIS and the transmission of remote alarm (RAI) and remote multiframe alarm signals. The National Use bits (Sa-bits) can be sourced from the E1-TRAN National Bits Codeword registers as 4-bit codewords aligned to the submultiframe. Alternatively, the Sa-bits may individually carry data links sourced from the internal HDLC controllers, or may be passed transparently from the BTPCM input. PCM output signals may be selected to conform to HDB3 or AMI line coding.
9.18 Transmit Elastic Store (TX-ELST)
The Transmit Elastic Store (TX-ELST) provides the ability to decouple the line timing from the backplane timing. The TX-ELST is required whenever the BTCLK and TCLKO clocks are not traceable to a common source. The elastic store function is in effect (with a nominal one frame delay) when: 1. BTCLK is an input (CMODE = 1) and the transmitter is loop timed to the receive recovered clock (PLLREF[1:0] = `b10, OCLKSEL1 = 0, OCLKSEL0 = 0). 2. BTCLK is an input (CMODE = 1) and the transmitter is clocked by TCLKI (OCLKSEL1 = 0, OCLKSEL0 = 1) or a jitter attenuated version of TCLKI (PLLREF[1:0] = `b11, OCLKSEL1 = 0, OCLKSEL0 = 0). 3. BTCLK is an output (CMODE = 0) referenced to the receive recovered clock (PLLREF[1:0] = `b10) and the transmitter is clocked by TCLKI (OCLKSEL1 = 0, OCLKSEL0 = 1).
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When the elastic store is being used, if the average frequency of the backplane data is greater than the average frequency of the line clock, the buffer will fill. Under this condition a controlled slip will occur upon the next frame boundary. The following frame of PCM data will be deleted. If the average frequency of the backplane data is less than the average frequency of the line clock, the buffer empty. Under this condition a controlled slip will occur upon the next frame boundary. The latest frame will be repeated. A slip operation is always performed on a frame boundary. The TX-ELST is upstream of the frame overhead insertion; therefore, frame slips do not corrupt the frame alignment signal. When the line timing is derived from BTCLK or BTCLK is an output, the elastic store is bypassed to eliminate the two frame delay.
9.19 Transmit Per-Channel Serial Controller (TPSC)
The Transmit Per-channel Serial Controller allows data and signaling trunk conditioning or idle code to be applied on the transmit DS-1 stream on a perchannel basis. It also allows per-channel control of zero code suppression, data inversion, and application of digital milliwatt. The Transmit Per-channel Serial Controller function is provided by a PerChannel Serial Controller (PCSC) block. The PCSC is a general purpose triple serializer. Data is sourced from three banks of thirty-two 8-bit registers, with each bank supporting a single serial output. The TPSC interfaces directly to the E1-TRAN and T1-XBAS blocks to provide serial streams for signaling control, idle code data and PCM data control. The registers are accessible from the P interface in an indirect address mode. The BUSY indication signal can be polled from an internal status register to check for completion of the current operation.
9.20 T1 Inband Loopback Code Generator (XIBC)
The T1 Inband Loopback Code Generator (XIBC) block generates a stream of inband loopback codes (IBC) to be inserted into a T1 data stream. The IBC stream consists of continuous repetitions of a specific code and can be either framed or unframed. When the XIBC is enabled to generate framed IBC, the framing bit overwrites the inband code pattern. The contents of the code and its length are programmable from 3 to 8 bits. The XIBC interfaces directly to the XBAS Basic Transmitter block.
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9.21
T1 Bit Oriented Code Generator (XBOC)
The T1 Bit Oriented Code Generator function is provided by the XBOC block. This block transmits 63 of the possible 64 bit oriented codes in the Facility Data Link channel in ESF framing format, as defined in ANSI T1.403-1989. The 64th code (111111) is similar to the HDLC Flag sequence and is used in the XBOC to disable transmission of any bit oriented codes. Bit oriented codes are transmitted on the Facility Data Link channel as a 16-bit sequence consisting of 8 ones, a zero, 6 code bits, and a trailing zero (111111110xxxxxx0) which is repeated as long as the code is not 111111. The transmitted bit oriented codes have priority over any data transmitted on the FDL except for ESF Yellow Alarm. The code to be transmitted is programmed by writing the code register.
9.22 HDLC Transmitters
The HDLC Transmit function is provided by the TDPR block. Three TDPR blocks are provided for flexible insertion of standardized data links:
* * * * * *
T1 ESF facility data link T1DM data link ISDN D-channel E1 Common Channel Signaling data link V5.1/V5.2 D-channel and C-channels. E1 Sa-bit data link
The TDPR is a general purpose HDLC transmitter. The TDPR is used under microprocessor control to transmit HDLC data frames. The TDPR performs all of the data serialization, CRC generation, zero-bit stuffing, as well as flag, idle, and abort sequence insertion. Data to be transmitted is provided by writing to a transmit data register. Upon completion of the frames, a CRC-CCITT frame check sequence is transmitted, followed by flag sequences. If the transmit data register underflows, an abort sequence is automatically transmitted. When enabled, the TDPR continuously transmits the flag sequence (01111110) until data is ready to be transmitted. Data bytes to be transmitted are written into the Transmit Data Register. The TDPR performs a parallel-to-serial conversion of each data byte and transmits it using one of two procedures.
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The default procedure provides automatic transmission of data once a complete packet is written. All complete packets of data will be transmitted. After the last data byte of a packet, the CRC word (if CRC insertion has been enabled) and a flag, or just a flag (if CRC insertion has not been enabled) is transmitted. The TDPR then returns to the transmission of flag characters until the next packet is available for transmission. While working in this mode, the user must only be careful to avoid overfilling the FIFO; underruns cannot occur unless the packet is greater than 128 bytes long. The TDPR will force transmission if the FIFO is filled up regardless of whether or not the packet has been completely written into the FIFO. The second procedure transmits data only when the FIFO depth has reached a user configured upper threshold. The TDPR will continue to transmit data until the FIFO depth has fallen below the upper threshold and the transmission of the last packet with data above the upper threshold has completed. In this mode, the user must be careful to avoid overruns and underruns. An interrupt can be generated once the FIFO depth has fallen below a user configured lower threshold as an indicator for the user to write more data. If there are more than five consecutive ones in the raw transmit data or in the CRC data, a zero is stuffed into the serial data output. This prevents the unintentional transmission of flag or abort characters. Abort characters can be continuously transmitted at any time by setting a control bit. During transmission, an underrun situation can occur if data is not written to the Transmit Data Register before the previous byte of a packet currently being transmitted has been depleted. In this case, an abort sequence is transmitted, and the controlling processor is notified via the UDR signal.
9.23 T1 Automatic Performance Report Generation
In compliance with the ANSI T1.231, T1.403 and T1.408 standards, a performance report is generated each second for T1 ESF applications. The report conforms to the HDLC protocol and is inserted into the ESF facility data link. The performance report can only be transmitted if TDPR #1 is configured to insert the ESF Facility Data Link and the PREN bit of the TDPR #1 Configuration register is logic 1. The performance report takes precedence over incompletely written packets, but it does not pre-empt packets already being transmitted. See the Operation section for details on the performance report encoding.
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9.24
Pulse Density Enforcer (XPDE)
The Pulse Density Enforcer function is provided by the XPDE block. Pulse density enforcement is enabled by a register bit within the XPDE. This block monitors the digital output of the transmitter and detects when the stream is about to violate the ANSI T1.403 12.5% pulse density rule over a moving 192-bit window. If a density violation is detected, the block can be enabled to insert a logic 1 into the digital stream to ensure the resultant output no longer violates the pulse density requirement. When the XPDE is disabled from inserting logic 1s, the digital stream from the transmitter is passed through unaltered.
9.25 Pseudo Random Pattern Generation and Detection
The Pseudo Random Sequence Generator/Processor (PRGD) is a software programmable test pattern generator, receiver and analyzer. Two types of test patterns (pseudo random and repetitive) conform to ITU-T O.151, O.152 and O.153 standards. The PRGD can be programmed to generate pseudo random patterns with lengths up to 32 bits or any user programmable bit pattern from 1 to 32 bits in length. In addition, the PRGD can insert single bit errors or a bit error rate between 10-1 to 10-7. The PRGD can be programmed to check for the generated pseudo random pattern. The PRGD can perform an auto synchronization to the expected pattern and accumulates the total number of bits received and the total number of bit errors in two 32-bit counters. The counters accumulate either over intervals defined by writes to the Pattern Detector registers or upon writes to the Global PMON Update Register. When an accumulation is forced, the holding registers are updated, and the counters reset to begin accumulating for the next interval. The counters are reset in such a way that no events are missed. The data is then available in the holding registers until the next accumulation.
9.26 Transmit Jitter Attenuator (TJAT)
The Transmit Jitter Attenuation function is provided by a digital phase lock loop and 80-bit deep FIFO. The TJAT receives jittery, dual-rail data in NRZ format on two separate inputs, which allows bipolar violations to pass through the block uncorrected. The incoming data streams are stored in a FIFO timed to the transmit clock (either BTCLK or the recovered clock). The respective input data emerges from the FIFO timed to the jitter attenuated clock (TCLKO) referenced to either TCLKI, BTCLK, or the recovered clock.
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The jitter attenuator generates the jitter-free 1.544 MHz or 2.048 MHz TCLKO output transmit clock by adjusting TCLKO's phase in 1/96 UI increments to minimize the phase difference between the generated TCLKO and input data clock to TJAT (either BTCLK or the recovered clock). Jitter fluctuations in the phase of the input data clock are attenuated by the phase-locked loop within TJAT so that the frequency of TCLKO is equal to the average frequency of the input data clock. For T1 applications, to best fit the jitter attenuation transfer function recommended by TR 62411, phase fluctuations with a jitter frequency above 5.7 Hz are attenuated by 6 dB per octave of jitter frequency. Wandering phase fluctuations with frequencies below 5.7 Hz are tracked by the generated TCLKO. In E1 applications, the corner frequency is 7.6 Hz. To provide a smooth flow of data out of TJAT, TCLKO is used to read data out of the FIFO. If the FIFO read pointer (timed to TCLKO) comes within one bit of the write pointer (timed to the input data clock, BTCLK or RSYNC), TJAT will track the jitter of the input clock. This permits the phase jitter to pass through unattenuated, inhibiting the loss of data.
Jitter Characteristics
The TJAT Block provides excellent jitter tolerance and jitter attenuation while generating minimal residual jitter. It can accommodate up to 61 UIpp of input jitter at jitter frequencies above 5.7 Hz (7.6 Hz for E1). For jitter frequencies below 5.7 Hz (7.6 Hz for E1), more correctly called wander, the tolerance increases 20 dB per decade. In most applications the TJAT Block will limit jitter tolerance at lower jitter frequencies only. For high frequency jitter, above 10 kHz for example, other factors such as clock and data recovery circuitry may limit jitter tolerance and must be considered. For low frequency wander, below 10 Hz for example, other factors such as slip buffer hysteresis may limit wander tolerance and must be considered. The TJAT block meets the stringent low frequency jitter tolerance requirements of AT&T TR 62411 and thus allows compliance with this standard and the other less stringent jitter tolerance standards cited in the references. The corner frequency in the jitter transfer response can be altered through programming. TJAT exhibits negligible jitter gain for jitter frequencies below 5.7 Hz (7.6 Hz for E1), and attenuates jitter at frequencies above 5.7 Hz (7.6 Hz for E1) by 20 dB per decade. In most applications, the TJAT block will determine jitter attenuation for higher jitter frequencies only. Wander, below 10 Hz for example, will essentially be passed unattenuated through TJAT. Jitter, above 10 Hz for example, will be attenuated as specified, however, outgoing jitter may be dominated by the generated residual jitter in cases where incoming jitter is insignificant. This generated residual jitter is directly related to the use of a
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1/96 UI phase adjustment quantum. TJAT meets the jitter attenuation requirements of AT&T TR 62411. The block allows the implied jitter attenuation requirements for a TE or NT1 given in ANSI Standard T1.408, and the implied jitter attenuation requirements for a type II customer interface given in ANSI T1.403 to be met.
Jitter Tolerance
Jitter tolerance is the maximum input phase jitter at a given jitter frequency that a device can accept without exceeding its linear operating range, or corrupting data. For TJAT, the input jitter tolerance is 61 Unit Intervals peak-to-peak (UIpp) with a worst case frequency offset of 354 Hz. It is 80 UIpp with no frequency offset. The frequency offset is the difference between the frequency of XCLK and that of the input data clock. Values above 2 kHz in the below graph are based on simulation results.
Figure 9 - TJAT Jitter Tolerance
100 28 JITTER AMPLITUDE, UI pp 10
JAT MIN.TOLER ANCE
61
1.0
acceptable unacceptable
0.4
0.1
0.01
1
10
100
1k
10k
100k
JITTER FREQUENCY, Hz
The accuracy of the XCLK frequency and that of the TJAT PLL reference input clock used to generate the jitter-free TCLKO output have an effect on the minimum jitter tolerance. Given that the TJAT PLL reference clock accuracy can
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be 200 Hz and that the XCLK input accuracy can be 100 ppm, the minimum jitter tolerance for various differences between the frequency of PLL reference clock and XCLK are shown in Figure 10.
Figure 10 - TJAT Minimum Jitter Tolerance vs. XCLK Accuracy
70 68 65 JAT MIN. JITTER TOLERANCE, 60 UI pp 55 66
61
MAX. FREQUENCY 100 OFFSET XCLK ACCURACY
200 0
250 32
300
354 100
Hz , ppm
Jitter Transfer
For T1 applications, the output jitter for jitter frequencies from 0 to 5.7 Hz (7.6 Hz for E1) is no more than 0.1 dB greater than the input jitter, excluding residual jitter. Jitter frequencies above 5.7 Hz (7.6 Hz for E1) are attenuated at a level of 6 dB per octave, as shown in Figure 11.
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Figure 11
- TJAT Jitter Transfer
0 -10 JITTER -20 GAIN dB -30 -40 -50 1 5.7 10 100 1k 10k
62411 min JAT response 62411 max 43802 max
JITTER FREQUENCY Hz
T1
In the non-attenuating mode, when the FIFO is within one UI of overrunning or under running, the tracking range is 1.48 MHz to 1.608 MHz. The guaranteed linear operating range for the jittered input clock is 1.544 MHz 200 Hz with worst case jitter (61 UIpp), and maximum system clock frequency offset ( 100 ppm). The nominal range is 1.544 MHz 963 Hz with no jitter or system clock frequency offset.
E1
In the non-attenuating mode, when the FIFO is within one UI of overrunning or under running, the tracking range is 2.13 MHz to 1.97 MHz. The guaranteed linear operating range for the jittered input clock is 2.048 MHz 300 Hz with worst case jitter (61 UIpp), and maximum system clock frequency offset ( 100 ppm). The nominal range is 2.048 MHz 1277 Hz with no jitter or system clock frequency offset.
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Jitter Generation
In the absence of input jitter, the output jitter shall be less than 0.025 UIpp. This complies with the AT&T TR 62411 requirement of less than 0.025 UIpp of jitter generation.
9.27 Timing Options (TOPS)
The Timing Options block provides a means of selecting the source of the reference signal for the transmit digital PLL and the clock source used to derive the output TCLKO signal.
9.28 Line Transmitter
The line transmitter generates Alternate Mark Inversion (AMI) transmit pulses suitable for use in the DSX-1 (short haul T1), short haul E1, long haul T1 and long haul E1 environments. The voltage pulses are produced by applying a current to a known termination (termination resistor plus line impedance). The use of current (instead of a voltage driver) simplifies transmit Input Return Loss (IRL), transmit short circuit protection (none needed) and transmit tri-stating. The output pulse shape is synthesized digitally with current digital-to-analog (DAC) converters which produce 24 samples per symbol. The current DAC's produce differential bipolar outputs that directly drive the TXTIP[1:0] and TXRING[1:0] pins. The current output is applied to a terminating resistor (optional) and line-coupling transformer in a differential manner, which when viewed from the line side of the transformer produce the output pulses at the required levels and insures a small positive to negative pulse imbalance. The pulse shape is user programmable. For T1 short haul, the cable length between the TLONG and the cross-connect (where the pulse template specifications are given) greatly affects the resulting pulse shapes. Hence, the data applied to the converter must account for different cable lengths. For CEPT E1 applications the pulse template is specified at the transmitter, thus only one setting is required. For T1 long haul with a LBO of 7.5 dB the previous bits effect what the transmitter must drive to compensate for inter-symbol interference; for LBO's of 15 dB or 22.5 dB the previous 3 or 4 bits effect what the transmitter must send out. Refer to the Operation section for details on creating the synthesized pulse shape.
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9.29
Backplane Receive Interface (BRIF)
The Backplane Receive Interface allows data to be presented to a backplane in either a 1.544 Mbit/s, 2.048 Mbit/s, 4.096 Mbit/s, 8.192 Mbit/s or sub-rate NxDS0 serial stream. All receive backplane signals are synchronous to BRCLK. BRCLK may be an output, in which case it is a jitter attenuated version of the recovered clock. If BRCLK is an input, it clocks the output of the frame slip buffer; therefore, it must be plesiochronous to the recovered clock. When configured to provide a 1.544 Mbit/s data rate, the block generates the output data stream on the BRPCM pin containing 24 channel bytes of data followed by a single bit containing the framing bit or parity over the 24 channels. The BRSIG output pin contains 24 bytes of signaling nibble data located in the least significant nibble of each byte followed by a single bit position representing the "place holder" for the framing bit or parity over the 24 channels. The framing alignment indication on the BRFP pin indicates the first bit of the 193-bit frame (or, optionally, the first bit of every second frame, the first bit of the first frame of the superframe, or every second superframe). When BRFP is an input, the data read from the frame slip buffer is aligned to it. In T1 mode, when configured to provide a 2.048 Mbit/s data rate, the block internally gaps the 2.048 MHz rate backplane clock to provide a serial PCM data on the BRPCM pin containing three channel bytes of data followed by one unused byte (can be logic 0 or logic 1). The signaling on the BRSIG pin is aligned to the least significant nibble of the associated channel on BRPCM. The frame alignment indication is provided on the BRFP pin, going high for one BRCLK cycle during the first bit of the unused byte, indicating the next data byte is the first channel of the frame, or the first channel of the first frame of the superframe. Alternatively, the PCM and signaling can be arranged in 24 contiguous timeslots, starting at the timeslot indicated by the BRFP pulse. In E1 mode, the 2.048 Mbit/s data stream consumes all timeslots of BRPCM. The BRSIG output pin present 30 bytes of signaling nibble data located in the least significant nibble of each byte. The framing alignment indication on the BRFP output can be configured to indicate the first bit of each 256-bit frame, the first bit of every other 256-bit frame, the first bit of the first frame of the CRC multiframe, the first bit of the first frame of the signaling multiframe or all overhead bits. If BRFP is configured as an input, the BRPCM and BRSIG can be forced to an specific alignment provided the elastic store is used (the RXELSTBYP register bit is logic 0). When configured for NxDS0 operation, no output clock edges are generated during the framing bit positions and idle channels.
PROPRIETARY AND CONFIDENTIAL
63
STANDARD PRODUCT DATA SHEET PMC-1970624 ISSUE 10
PM4351 COMET
COMBINED E1/T1 TRANSCEIVER
As a programming option, the data stream bit and timeslot alignment relative to BRFP can be modified for Concentration Highway Interface (CHI) applications. When configured for a multiplexed backplane, the two or four sets of PCM and signaling streams are byte-interleaved into a 4.096 Mbit/s or 8.192 Mbit/s serial stream.
9.30 Backplane Transmit Interface (BTIF)
The Backplane Transmit Interface allows data to be taken from a backplane in either a 1.544 Mbit/s, 2.048 Mbit/s, 4.096 Mbit/s, 8.192 Mbit/s or sub-rate NxDS0 serial stream. When configured to receive a 1.544 Mbit/s data rate stream, the input data stream on the BTPCM pin to is expected to contain 24 channel bytes of data followed by a single bit location for the framing bit or optional parity over the previous 24 channels. The BTSIG input pin must contain 24 bytes of signaling nibble data located in the least significant nibble of each byte followed by a single bit position for the framing bit or optional parity over the previous frame. The framing alignment indication on the BTFP input must indicate the framing bit position of the 193-bit frame (or, optionally, the framing bit position of the first frame of the superframe). In T1 mode, when configured to provide a 2.048 Mbit/s data rate, the block expects serial PCM data on the BTPCM pin to contain three channel bytes of data followed by one unused byte. The signaling on the BTSIG pin must be aligned to the least significant nibble of the associated channel on BTPCM. The frame alignment indication is expected on the BTFP pin, going to high during the first bit of the unused byte, indicating the next data byte is the first channel of the frame. Alternatively, the PCM and signaling can be arranged in 24 contiguous timeslots, starting at the timeslot indicated by the BTFP pulse. In E1 mode, the 2.048 Mbit/s data stream consumes all timeslots of BRPCM. The BTSIG input presents 30 bytes of signaling nibble data located in the least significant nibble of each timeslot. The framing alignment indication on the BTFP pin can be configured to indicate the first bit of each 256-bit frame or the first bit of the first frame of the CRC multiframe and signaling multiframes. BTCLK can be configured as an output, in which case, BTCLK is generated from TCLKO. When configured for NxDS0 operation, no output clock edges are generated during the framing bit positions and idle channels. BTFP can be configured as an output, in which case, the COMET dictates the frame alignment.
PROPRIETARY AND CONFIDENTIAL
64
STANDARD PRODUCT DATA SHEET PMC-1970624 ISSUE 10
PM4351 COMET
COMBINED E1/T1 TRANSCEIVER
As a programming option, the data stream bit and timeslot alignment relative to BTFP can be modified for Concentration Highway Interface (CHI) applications. When configured for a multiplexed backplane, one of two or four sets of PCM and signaling streams are extracted from the byte-interleaved 4.096 Mbit/s or 8.192 Mbit/s serial stream.
9.31 JTAG Test Access Port
The JTAG Test Access Port block provides JTAG support for boundary scan. The standard JTAG EXTEST, SAMPLE, BYPASS, IDCODE and STCTEST instructions are supported. The COMET revision E identification code is 443510CD hexadecimal. The revision F code is 543510CD.
9.32 Microprocessor Interface (MPIF)
The Microprocessor Interface allows the COMET to be configured, controlled and monitored via internal registers.
PROPRIETARY AND CONFIDENTIAL
65
STANDARD PRODUCT DATA SHEET PMC-1970624 ISSUE 10
PM4351 COMET
COMBINED E1/T1 TRANSCEIVER
10 10.1
REGISTER DESCRIPTION Normal Mode Register Memory Map Table 16 Addr - Normal Mode Register Memory Map Register
000H 001H 002H 003H 004H 005H 006H 007H 008H 009H 00AH 00BH 00CH 00DH 00EH 00FH 010H 011H 012H 013H 014H 015H 016H 017H
Global Configuration Clock Monitor Receive Options Receive Line Interface Configuration Transmit Line Interface Configuration Transmit Framing and Bypass Options Transmit Timing Options Interrupt Source #1 Interrupt Source #2 Interrupt Source #3 Master Diagnostics Master Test Analog Diagnostics Revision/Chip ID/Global PMON Update Reset PRGD Positioning/Control and HDLC Control CDRC Configuration CDRC Interrupt Enable CDRC Interrupt Status CDRC Alternate Loss of Signal RJAT Interrupt Status RJAT Reference Clock Divisor (N1) Control RJAT Output Clock Divisor (N2) Control RJAT Configuration
PROPRIETARY AND CONFIDENTIAL
66
STANDARD PRODUCT DATA SHEET PMC-1970624 ISSUE 10
PM4351 COMET
COMBINED E1/T1 TRANSCEIVER
Addr
Register
018H 019H 01AH 01BH 01CH 01DH 01EH 01FH 020H 021H 022H-023H 024H-027H 028H 029H 02AH 02BH 02CH 02DH 02EH-02FH 030H 031H 032H 033H 034H 035H-037H 038H 039H 03AH 03BH
TJAT Interrupt Status TJAT Reference Clock Divisor (N1) Control TJAT Output Clock Divisor (N2) Control TJAT Configuration RX-ELST Configuration RX-ELST Interrupt Enable/Status RX-ELST Idle Code RX-ELST Reserved TX-ELST Configuration TX-ELST Interrupt Enable/Status TX-ELST Reserved Reserved RXCE Receive Data Link 1 Control RXCE Receive Data Link 1 Bit Select RXCE Receive Data Link 2 Control RXCE Receive Data Link 2 Bit Select RXCE Receive Data Link 3 Control RXCE Receive Data Link 3 Bit Select RXCE Reserved BRIF Receive Backplane Configuration BRIF Receive Backplane Frame Pulse Configuration BRIF Receive Backplane Parity/F-Bit Configuration BRIF Receive Backplane Time Slot Offset BRIF Receive Backplane Bit Offset BRIF Receive Backplane Reserved TXCI Transmit Data Link 1 Control TXCI Transmit Data Link 1 Bit Select TXCI Transmit Data Link 2 Control TXCI Transmit Data Link 2 Bit Select
PROPRIETARY AND CONFIDENTIAL
67
STANDARD PRODUCT DATA SHEET PMC-1970624 ISSUE 10
PM4351 COMET
COMBINED E1/T1 TRANSCEIVER
Addr
Register
03CH 03DH 03EH-03FH 040H 041H 042H 043H 044H 045H 046H 047H 048H 049H 04AH 04BH 04CH 04DH 04EH 04FH 050H 051H 052H 053H 054H 055H 056H 057H 058H
TXCI Transmit Data Link 3 Control TXCI Transmit Data Link 3 Bit Select TXCI Reserved BTIF Transmit Backplane Configuration BTIF Transmit Backplane Frame Pulse Configuration BTIF Transmit Backplane Parity Configuration and Status BTIF Transmit Backplane Time Slot Offset BTIF Transmit Backplane Bit Offset Register BTIF Transmit Backplane Reserved BTIF Transmit Backplane Reserved BTIF Transmit Backplane Reserved T1 FRMR Configuration T1 FRMR Interrupt Enable T1 FRMR Interrupt Status Reserved IBCD Configuration IBCD Interrupt Enable/Status IBCD Activate Code IBCD Deactivate Code SIGX Configuration/Change of Signaling State SIGX P Access Status/Change of Signaling State SIGX Channel Indirect Address/Control/ Change of Signaling State SIGX Channel Indirect Data Buffer/Change of Signaling State T1 XBAS Configuration T1 XBAS Alarm Transmit T1 XIBC Control T1 XIBC Loopback Code PMON Interrupt Enable/Status
PROPRIETARY AND CONFIDENTIAL
68
STANDARD PRODUCT DATA SHEET PMC-1970624 ISSUE 10
PM4351 COMET
COMBINED E1/T1 TRANSCEIVER
Addr
Register
059H 05AH 05BH 05CH 05DH 05EH 05FH 060H 061H 062H 063H 064H 065H 066H 067H 068H 069H 06AH 06BH 06CH 06DH 06EH 06FH 070H 071H 072H 073H 074H-077H 078H
PMON Framing Bit Error Count PMON OOF/COFA/Far End Block Error Count (LSB) PMON OOF/COFA/Far End Block Error Count (MSB) PMON Bit Error/CRCE Count (LSB) PMON Bit Error/CRCE Count (MSB) PMON LCV Count (LSB) PMON LCV Count (MSB) T1 ALMI Configuration T1 ALMI Interrupt Enable T1 ALMI Interrupt Status T1 ALMI Alarm Detection Status T1 PDVD Reserved T1 PDVD Interrupt Enable/Status T1 XBOC Reserved T1 XBOC Code T1 XPDE Reserved T1 XPDE Interrupt Enable/Status T1 RBOC Enable T1 RBOC Code Status TPSC Configuration TPSC P Access Status TPSC Channel Indirect Address/Control TPSC Channel Indirect Data Buffer RPSC Configuration RPSC P Access Status RPSC Channel Indirect Address/Control RPSC Channel Indirect Data Buffer Reserved T1 APRM Configuration/Control
PROPRIETARY AND CONFIDENTIAL
69
STANDARD PRODUCT DATA SHEET PMC-1970624 ISSUE 10
PM4351 COMET
COMBINED E1/T1 TRANSCEIVER
Addr
Register
079H 07AH 07BH 07CH 07DH 07EH 07FH 080H 081H 082H 083H 084H 085H 086H 087H 088H-08BH 08CH 08DH 08EH 08FH 090H 091H 092H 093H 094H 095H 096H 097H 098H
T1 APRM Manual Load T1 APRM Interrupt Status T1 APRM One Second Content Octet 2 T1 APRM One Second Content Octet 3 T1 APRM One Second Content Octet 4 T1 APRM One Second Content MSB (Octet 5) T1 APRM One Second Content LSB (Octet 6) E1 TRAN Configuration E1 TRAN Transmit Alarm/Diagnostic Control E1 TRAN International Control E1 TRAN Extra Bits Control E1 TRAN Interrupt Enable E1 TRAN Interrupt Status E1 TRAN National Bit Codeword Select E1 TRAN National Bit Codeword Reserved T1 FRMR Reserved T1 FRMR Reserved Reserved Reserved E1 FRMR Frame Alignment Options E1 FRMR Maintenance Mode Options E1 FRMR Framing Status Interrupt Enable E1 FRMR Maintenance/Alarm Status Interrupt Enable E1 FRMR Framing Status Interrupt Indication E1 FRMR Maintenance/Alarm Status Interrupt Indication E1 FRMR Framing Status E1 FRMR Maintenance/Alarm Status E1 FRMR International/National Bits
PROPRIETARY AND CONFIDENTIAL
70
STANDARD PRODUCT DATA SHEET PMC-1970624 ISSUE 10
PM4351 COMET
COMBINED E1/T1 TRANSCEIVER
Addr
Register
099H 09AH 09BH 09CH 09DH 09EH 09FH 0A0H-0A7H 0A8H 0A9H 0AAH 0ABH 0ACH 0ADH 0AEH 0AFH 0B0H 0B1H 0B2H 0B3H 0B4H 0B5H 0B6H 0B7H 0B8H 0B9H 0BAH 0BBH 0BCH
E1 FRMR CRC Error Count - LSB E1 FRMR CRC Error Count - MSB E1 FRMR National Bit Codeword Interrupt Enables E1 FRMR National Bit Codeword Interrupts E1 FRMR National Bit Codewords E1 FRMR Frame Pulse/Alarm Interrupt Enables E1 FRMR Frame Pulse/Alarm Interrupt Reserved TDPR #1 Configuration TDPR #1 Upper Transmit Threshold TDPR #1 Lower Transmit Threshold TDPR #1 Interrupt Enable TDPR #1 Interrupt Status/UDR Clear TDPR #1 Transmit Data Reserved Reserved TDPR #2 Configuration TDPR #2 Upper Transmit Threshold TDPR #2 Lower Transmit Threshold TDPR #2 Interrupt Enable TDPR #2 Interrupt Status/UDR Clear TDPR #2 Transmit Data Reserved Reserved TDPR #3 Configuration TDPR #3 Upper Transmit Threshold TDPR #3 Lower Transmit Threshold TDPR #3 Interrupt Enable TDPR #3 Interrupt Status/UDR Clear
PROPRIETARY AND CONFIDENTIAL
71
STANDARD PRODUCT DATA SHEET PMC-1970624 ISSUE 10
PM4351 COMET
COMBINED E1/T1 TRANSCEIVER
Addr
Register
0BDH 0BEH 0BFH 0C0H 0C1H 0C2H 0C3H 0C4H 0C5H 0C6H 0C7H 0C8H 0C9H 0CAH 0CBH 0CCH 0CDH 0CEH 0CFH 0D0H 0D1H 0D2H 0D3H 0D4H 0D5H 0D6H 0D7H 0D8H 0D9H
TDPR #3 Transmit Data Reserved Reserved RDLC #1 Configuration RDLC #1 Interrupt Control RDLC #1 Status RDLC #1 Data RDLC #1 Primary Address Match RDLC #1 Secondary Address Match Reserved Reserved RDLC #2 Configuration RDLC #2 Interrupt Control RDLC #2 Status RDLC #2 Data RDLC #2 Primary Address Match RDLC #2 Secondary Address Match Reserved Reserved RDLC #3 Configuration RDLC #3 Interrupt Control RDLC #3 Status RDLC #3 Data RDLC #3 Primary Address Match RDLC #3 Secondary Address Match CSU Configuration CSU Reserved RLPS Indirect Data Register RLPS Indirect Data Register
PROPRIETARY AND CONFIDENTIAL
72
STANDARD PRODUCT DATA SHEET PMC-1970624 ISSUE 10
PM4351 COMET
COMBINED E1/T1 TRANSCEIVER
Addr
Register
0DAH 0DBH 0DCH 0DDH-0DFH 0E0H 0E1H 0E2H 0E3H 0E4H 0E5H 0E6H 0E7H 0E8H 0E9H 0EAH 0EBH 0ECH 0EDH 0EEH 0EFH 0F0H 0F1H 0F2H 0F3H 0F4H 0F5H 0F6H 0F7H 0F8H
RLPS Indirect Data Register RLPS Indirect Data Register RLPS Equalizer Voltage Reference RLPS Reserved PRGD Control PRGD Interrupt Enable/Status PRGD Shift Register Length PRGD Tap PRGD Error Insertion PRGD Reserved PRGD Reserved PRGD Reserved PRGD Pattern Insertion #1 PRGD Pattern Insertion #2 PRGD Pattern Insertion #3 PRGD Pattern Insertion #4 PRGD Pattern Detector #1 PRGD Pattern Detector #2 PRGD Pattern Detector #3 PRGD Pattern Detector #4 XLPG Line Driver Configuration XLPG Control/Status XLPG Pulse Waveform Storage Write Address XLPG Pulse Waveform Storage Data XLPG Analog Test Positive Control XLPG Analog Test Negative Control XLPG Fuse Data Select XLPG Reserved RLPS Configuration and Status
PROPRIETARY AND CONFIDENTIAL
73
STANDARD PRODUCT DATA SHEET PMC-1970624 ISSUE 10
PM4351 COMET
COMBINED E1/T1 TRANSCEIVER
Addr
Register
0F9H 0FAH 0FBH 0FCH 0FDH 0FEH 0FFH 100H-1FFH
RLPS ALOS Detection/Clearance Threshold RLPS ALOS Detection Period RLPS ALOS Clearance Period RLPS Equalization Indirect Address RLPS Equalization Read/WriteB Select RLPS Equalizer Loop Status and Control RLPS Equalizer Configuration Reserved for Test
PROPRIETARY AND CONFIDENTIAL
74
STANDARD PRODUCT DATA SHEET PMC-1970624 ISSUE 10
PM4351 COMET
COMBINED E1/T1 TRANSCEIVER
11
NORMAL MODE REGISTER DESCRIPTION
Normal mode registers are used to configure and monitor the operation of the COMET. Normal mode registers (as opposed to test mode registers) are selected when A[8] is low.
Notes on Normal Mode Register Bits:
1. Writing values into unused register bits has no effect. Reading back unused bits can produce either a logic 1 or a logic 0; hence, unused register bits should be masked off by software when read. 2. All configuration bits that can be written into can also be read back. This allows the processor controlling the COMET to determine the programming state of the chip. 3. Writeable normal mode register bits are cleared to zero upon reset unless otherwise noted. 4. Writing into read-only normal mode register bit locations does not affect COMET operation unless otherwise noted.
PROPRIETARY AND CONFIDENTIAL
75
STANDARD PRODUCT DATA SHEET PMC-1970624 ISSUE 10
PM4351 COMET
COMBINED E1/T1 TRANSCEIVER
Register 000H: Global Configuration Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PIO_OE:
R/W R/W R/W R/W R/W R/W R/W R/W
PIO_OE PIO IBCD_IDLE RSYNC_ALOSB OOSMFAIS TRKEN RXMTKC E1/T1B
1 0 0 0 0 0 0 0
The programmable I/O output enable, PIO_OE, bit controls the PIO pin. When PIO_OE is logic 1, the PIO pin is configured as an output and driven by the COMET. When PIO_OE is logic 0, the PIO pin is configured as an input. Upon reset, the PIO pin is configured as an output. PIO: The programmable I/O, PIO, bit controls/reflects the state of the PIO pin. When the PIO pin is configured as an output, the PIO bit controls the state of the PIO pin. When the PIO pin is configured as an input, the PIO bit reflects the state of the PIO pin. Upon reset, the PIO pin has an output value of logic 0. OOSMFAIS: In E1 mode, this bit controls the receive backplane signaling trunk conditioning in an out of signaling multiframe condition. If OOSMFAIS is set to a logic 0, an OOSMF indication from the E1-FRMR does not affect the BRSIG output. When OOSMFAIS is a logic 1, an OOSMF indication from the E1-FRMR will cause the BRSIG output to be set to all 1's. RSYNC_ALOSB: The RSYNC_ALOSB bit controls the source of the loss of signal condition used to control the behaviour of the receive reference presented on the RSYNC. If RSYNC_ALOSB is a logic 0, analog loss of signal is used. If RSYNC_ALOSB is a logic 1, digital loss of signal is used. When COMET is in a loss of signal state, the RSYNC output is derived from XCLK. When
PROPRIETARY AND CONFIDENTIAL
76
STANDARD PRODUCT DATA SHEET PMC-1970624 ISSUE 10
PM4351 COMET
COMBINED E1/T1 TRANSCEIVER
COMET is not in a loss of signal state, the RSYNC output is derived from the recovered receiver clock. IBCD_IDLE: When the IBCD_IDLE bit is set to logic 1 gaps the data to the inband code detector (IBCD) block during the framing bit. This allows the IBCD to be used to detect an idle code that is inserted only in the payload of the receive DS1 PCM stream. The IBCD must still be programmed to detect the desired pattern, and otherwise operates unchanged. The IBCD_IDLE bit is only valid in T1 mode. TRKEN: The TRKEN bit enables receive trunk conditioning upon an out-of-frame condition. If TRKEN is logic 1, the contents of the RX-ELST Idle Code register are inserted into all time slots (including TS0 and TS16) of BRPCM if the framer is out-of-basic frame (i.e. the OOF status bit is logic 1). The TRKEN bit only has effect if RXELSTBYP bit is logic 0. If TRKEN is a logic 0, receive trunk conditioning can still be performed on a per-timeslot basis via the RPSC Data Trunk Conditioning and Signaling Trunk Conditioning registers. RXMTKC: The RXMTKC bit allows global trunk conditioning to be applied to the received data and signaling streams, BRPCM and BRSIG. When RXMTKC is set to logic 1, the data on BRPCM for each channel is replaced with the data contained in the data trunk conditioning registers within RPSC; similarly, the signaling data on BRSIG for each channel is replaced with the data contained in the signaling trunk conditioning registers. When RXMTKC is set to logic 0, the data and signaling signals are modified on a per-channel basis in accordance with the control bits contained in the per-channel control registers within the RPSC. E1/T1B: The E1/T1B bit selects the operating mode of COMET. If E1/T1B is logic 1, the 2.048 Mbit/s E1 mode is selected. If E1/T1B is logic 0, the 1.544 Mbit/s T1 mode is selected.
PROPRIETARY AND CONFIDENTIAL
77
STANDARD PRODUCT DATA SHEET PMC-1970624 ISSUE 10
PM4351 COMET
COMBINED E1/T1 TRANSCEIVER
Register 001H: Clock Monitor Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R R R R R
Unused Unused Unused XCLKA BTCLKA TCLKIA BRCLKA RCLKIA
X X X X X X X X
When a monitored clock signal makes a low to high transition, the corresponding register bit is set high. The bit will remain high until this register is read, at which point all the bits in this register are cleared. A lack of transitions is indicated by the corresponding register bit reading low. This register should be read at periodic intervals to detect clock failures. BTCLKA: The BTCLK active (BTCLKA) bit detects low to high transitions on the BTCLK input. BTCLKA is set high on a rising edge of BTCLK, and is set low when this register is read. TCLKIA: The TCLKI active (TCLKIA) bit detects low to high transitions on the TCLKI input. TCLKIA is set high on a rising edge of TCLKI, and is set low when this register is read. BRCLKA: The BRCLK active (BRCLKA) bit detects low to high transitions on the BRCLK input. BRCLKA is set high on a rising edge of BRCLK, and is set low when this register is read. RCLKIA: The RCLKI active (RCLKA) bit detects low to high transitions on the RCLKI input. RCLKIA is set high on a rising edge of RCLKI, and is set low when this register is read.
PROPRIETARY AND CONFIDENTIAL
78
STANDARD PRODUCT DATA SHEET PMC-1970624 ISSUE 10
PM4351 COMET
COMBINED E1/T1 TRANSCEIVER
XCLKA: The XCLK active (XCLKA) bit detects for low to high transitions on the XCLK input. XCLKA is set high on a rising edge of XCLK, and is set low when this register is read.
PROPRIETARY AND CONFIDENTIAL
79
STANDARD PRODUCT DATA SHEET PMC-1970624 ISSUE 10
PM4351 COMET
COMBINED E1/T1 TRANSCEIVER
Register 002H: Receive Options Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
R/W R/W R/W R/W R/W R/W R/W R/W
RJATBYP UNF RXELSTBYP RSYNC_MEM RSYNCSEL WORDERR CNTNFAS CCOFA
1 0 0 0 0 0 0 0
This register allows software to configure the receive functions of each framer. RJATBYP: The RJATBYP bit disables jitter attenuation in the receive direction. When receive jitter attenuation is not being used, setting RJATBYP to logic 1 will reduce the latency through the receiver section by typically 40 bits. When RJATBYP is set to logic 0, the RSYNC output and the BRCLK output (if BRCLK is configured to be an output by setting the CMODE bit of the Receive Backplane Configuration register to logic 0), are jitter attenuated. When the RJAT is bypassed, RSYNC and BRCLK are not jitter attenuated. UNF: The UNF bit allows the framer to operate with unframed DS-1 or E1 data. When UNF is set to logic 1, the framer is disabled (both the T1-FRMR and E1-FRMR are held reset) and the recovered data passes through the receiver section of the framer without frame or channel alignment. While UNF is set to logic 1, the Alarm Integrator continues to operate and detects and integrates AIS alarm. When UNF is set to logic 0, the framer operates normally, searching for frame alignment on the incoming data. When UNF is a logic 1, the BRFP pin (if configured as an output) is held low. RXELSTBYP: The RXELSTBYP bit allows the Receive Elastic Store (RX-ELST) to be bypassed, eliminating the one frame delay incurred through the RX-ELST. When set to logic 1, the received data and clock inputs to RX-ELST are internally routed directly to the RX-ELST output.
PROPRIETARY AND CONFIDENTIAL
80
STANDARD PRODUCT DATA SHEET PMC-1970624 ISSUE 10
PM4351 COMET
COMBINED E1/T1 TRANSCEIVER
If RXELSTBYP is logic 1, the CMODE bit of the Receive Backplane Configuration register must be logic 0 and the FPMODE bit of the Receive Backplane Frame Pulse Configuration register must be logic 0. RSYNC_MEM: The RSYNC_MEM bit controls the RSYNC output under a loss of signal condition (as determined by the RSYNC_ALOSB register bit). When RSYNC_MEM is a logic 1, the RSYNC output is held high during a loss of signal condition. When RSYNC_MEM is a logic 0, the RSYNC output is derived from XCLK during a loss of signal condition. RSYNCSEL: The RSYNCSEL bit selects the frequency of the receive reference presented on the RSYNC output. If RSYNCSEL is a logic 1, RSYNC will be an 8 kHz clock. If RSYNCSEL is a logic 0, RSYNC will be an 1.544 MHz (T1) or 2.048 MHz (E1) clock. WORDERR: In E1 mode, the WORDERR bit determines how frame alignment signal (FAS) errors are reported. When WORDERR is logic 1, one or more errors in the seven bit FAS word results in a single framing error count. When WORDERR is logic 0, each error in a FAS word results in a single framing error count. CNTNFAS: In E1 mode, when the CNTNFAS bit is a logic 1, a zero in bit 2 of time slot 0 of non-frame alignment signal (NFAS) frames results in an increment of the framing error count. If WORDERR is also a logic 1, the word is defined as the eight bits consisting of the seven-bit FAS pattern and bit 2 of time slot 0 of the next NFAS frame. When the CNTNFAS bit is a logic 0, only errors in the FAS affect the framing error count. CCOFA The CCOFA bit determines whether the PMON counts Change-Of-Frame Alignment (COFA) events or out-of-frame (OOF ) events. When CCOFA is set to logic 1, COFA events are counted by PMON. When CCOFA is set to logic 0, OOF events are counted by PMON. The CCOFA bit is only valid in T1 mode.
PROPRIETARY AND CONFIDENTIAL
81
STANDARD PRODUCT DATA SHEET PMC-1970624 ISSUE 10
PM4351 COMET
COMBINED E1/T1 TRANSCEIVER
Register 003H: Receive Line Interface Configuration Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
R/W R/W R/W R/W R/W R/W R/W R/W
AUTOYELLOW AUTORED AUTOOOF AUTOAIS RUNI BPV RDATINV RFALL
0 0 0 0 0 0 0 0
AUTOYELLOW: In T1 mode, when the AUTOYELLOW bit is set to logic 1, whenever the alarm integrator declares a Red alarm in the receive direction, Yellow alarm will be transmitted to the far end. When AUTOYELLOW is set to logic 0, Yellow alarm will only be transmitted when the XYEL bit is set in the T1-XBAS Alarm Transmit Register. Note that the Red alarm is not deasserted on detection of AIS. In E1 mode, when the AUTOYELLOW bit is set to logic 1, The RAI bit in the transmit stream is set to a logic 1 for the duration of a loss of frame alignment or AIS. The G706ANNBRAI bit of the Transmit Framing and Bypass Options register optionally also allows for the transmission of RAI when CRC-to-nonCRC interworking has been established. When AUTOYELLOW is set to logic 0, RAI will only be transmitted when the RAI bit is set in the E1-TRAN Transmit Alarm/Diagnostic Control register. AUTORED: The AUTORED bit allows global trunk conditioning to be applied to the receive data and signaling streams, BRPCM and BRSIG, immediately upon declaration of Red carrier failure alarm. When AUTORED is set to logic 1, the data on BRPCM for each channel is replaced with the data contained in the Data Trunk Conditioning registers within RPSC and the data on BRSIG for each channel is replaced with the data contained in the Signaling Trunk Conditioning registers within the RPSC while Red CFA is declared. When AUTORED is set to logic 0, the receive data is not automatically conditioned when Red CFA is declared.
PROPRIETARY AND CONFIDENTIAL
82
STANDARD PRODUCT DATA SHEET PMC-1970624 ISSUE 10
PM4351 COMET
COMBINED E1/T1 TRANSCEIVER
AUTOOOF: The AUTOOOF bit allows global trunk conditioning to be applied to the receive data stream, BRPCM, immediately upon declaration of out of frame (OOF). When AUTOOOF is set to logic 1, while OOF is declared, the data on BRPCM for each channel is replaced with the data contained in the data trunk conditioning registers within RPSC. When AUTOOOF is set to logic 0, the ingress data is not automatically conditioned by RPSC when OOF is declared. However, if the RX-ELST is not bypassed, the RX-ELST trouble code will still be inserted in channel data while OOF is declared if the TRKEN register bit is logic 1. RPSC data and signaling trunk conditioning overwrites the RX-ELST trouble code. AUTOAIS: If the AUTOAIS bit is logic 1, AIS is inserted in the receive path and the signaling is frozen for the duration of a loss of signal condition. If AUTOAIS is logic 0, AIS may be inserted manually via the RAIS register bit. RUNI: The RUNI bit selects the source of receive data. If RUNI is a logic 1, the receive data stream and clock are expected to be presented on the RDAT and RCLKI inputs, respectively. If RUNI is a logic 0, the receive data and clock will be recovered from the analog RXTIP and RXRING inputs. These inputs will typically be connected to a signal transformer and may exhibit the attenuation and dispersion characteristics of short or long haul lines. BPV: In T1 mode, the BPV bit enables only bipolar violations to indicate line code violations and be accumulated in the PMON LCV Count Registers. When BPV is set to logic 1, BPVs (which are not part of a valid B8ZS signature if B8ZS line coding is used) generate an LCV indication and increment the PMON LCV counter. When BPV is set to logic 0, both BPVs (which are not part of a valid B8ZS signature if B8ZS line coding is used) and excessive zeros (EXZ) generate an LCV indication and increment the PMON LCV counter. Excessive zeros is a sequence of zeros greater than fifteen bits long for an AMI-coded signal and greater than seven bits long for a B8ZS-coded signal. In E1 mode, the BPV bit enables only bipolar violations to indicate line code violations and be accumulated in the PMON LCV Count Registers. (The O162 bit in the CDRC Configuration register provides two E1 LCV definitions.) When BPV is set to logic 1, BPVs (which are not part of a valid HDB3 signature if HDB3 line coding is used) generate an LCV indication and
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PM4351 COMET
COMBINED E1/T1 TRANSCEIVER
increment the PMON LCV counter. When BPV is set to logic 0, both BPVs (which are not part of a valid HDB3 signature if HDB3 line coding is used) and excessive zeros (EXZ) generate an LCV indication and increment the PMON LCV counter. Excessive zeros is a sequence of zeros greater than four bits long. RDATINV: When RDATINV is set to logic 1, the receive digital interface assumes the RDAT input is active low. When RDATINV is set to logic 0, the interface assumes the RDAT input is active high. This bit only has effect if the RUNI bit is logic 1. RFALL: When RFALL is set to logic 1, the RDAT signal is sampled by the falling RCLKI edge. When RFALL is set to logic 0, the RDAT signal is sampled by the rising RCLKI edge. This bit only has effect if the RUNI bit is logic 1.
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PM4351 COMET
COMBINED E1/T1 TRANSCEIVER
Register 004H: Transmit Line Interface Configuration Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
R/W R/W R/W R/W R/W R/W
TJATBYP TAISEN TAUXP TDATINV TUNI Unused TRISE Unused
0 0 0 0 0 X 0 X
This register enables the transmit interface to generate the required digital output waveform format. TJATBYP: The TJATBYP bit enables the transmit jitter attenuator's FIFO to be removed from the transmit data path. When transmit jitter attenuation is not being used, setting TJATBYP to logic 1 will reduce the latency through the transmitter section by typically 40 bits. TAISEN: The TAISEN bit enables the interface to generate an unframed all-ones AIS alarm on the TXTIP, TXRING and TDAT pins. When TAISEN is set to logic 1 and TUNI is set to logic 0, the bipolar TXTIP and TXRING outputs are forced to pulse alternately, creating an all-ones signal; when TAISEN and TUNI are both set to logic 1, the unipolar TDAT output is forced to all-ones. The transition to transmitting AIS on the TXTIP and TXRING outputs is done in such a way as to not introduce any bipolar violations. The TAISEN bit only takes effect when the AISE bit of the XLPG Control/Status register is logic 1. The diagnostic loopback point is upstream of this AIS insertion point. TAUXP: The TAUXP bit enables the interface to generate an unframed alternating zeros and ones (i.e. 010101...) auxiliary pattern (AUXP) on the TXTIP, TXRING and TDAT pins. When TAUXP is set to logic 1 and TUNI is set to
PROPRIETARY AND CONFIDENTIAL
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PM4351 COMET
COMBINED E1/T1 TRANSCEIVER
logic 0, the bipolar TXTIP and TXRING outputs are forced to pulse alternately every other cycle; when TAUXP and TUNI are both set to logic 1, the unipolar TDAT output is forced to toggle every cycle. The transition to transmitting AUXP on the TXTIP and TXRING outputs is done in such a way as to not introduce any bipolar violations. The diagnostic loopback point is upstream of this AUXP insertion point. TDATINV: The TDATINV bit enables the digital transmit interface to logically invert the TDAT signal. When TDATINV is set to logic 1, the TDAT output is active low. When TDATINV is set to logic 0, the TDAT output is active high. TDATINV only has effect when TUNI is a logic 1. TUNI: The TUNI bit determines which interface presents the transmit data. If TUNI is a logic 1, the transmit data is presented as TTL compatible unipolar data on the TDAT output with an associated clock on the TCLKO output and frame alignment pulse on the TFP output. The transmit line interface is held reset; therefore, the TXTIP and TXRING outputs are high-impedance. If TUNI is a logic 0, the transmit data is presented on the TXTIP and TXRING as pulses suitable for driving a transformer directly and the TDAT, TFP and TCLKO outputs are held low. TRISE: When TRISE is set to logic 1, the interface is enabled to update the TDAT and TFP output pins on the rising edge of TCLKO. When TRISE is set to logic 0, the interface is enabled to update the outputs on the falling edge of TCLKO.
PROPRIETARY AND CONFIDENTIAL
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PM4351 COMET
COMBINED E1/T1 TRANSCEIVER
Register 005H: Transmit Framing and Bypass Options Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
R/W R/W R/W R/W R/W R/W R/W R/W
PATHCRC G706ANNBRAI SIGAEN OOCMFE0 FDIS FBITBYP CRCBYP FDLBYP
0 0 0 0 0 0 0 0
This register allows software to configure the bypass and framing options of the transmitter, the use of the Signaling Alignment block, and controls the global transmit framing disable. PATHCRC: This bit only has effect in E1 mode. When in E1 mode, the PATHCRC bit allows upstream block errors to be preserved in the transmit CRC bits. If PATHCRC is a logic 1, the CRC-4 bits are modified to reflect any bit values in BTPCM which have changed prior to transmission. When PATHCRC is set to logic 0, a new CRC-4 value overwrites the incoming CRC-4 word. For the PATHCRC bit to be effective, the FPTYP bit of the Transmit Backplane Frame Pulse Configuration register must be a logic 1; otherwise, the identification of the incoming CRC-4 bits would be impossible. The PATHCRC bit only takes effect if the GENCRC bit of the E1-TRAN Configuration register is a logic 1 and either the INDIS or FDIS bit in the same register are set to logic 1. G706ANNBRAI: When in E1 mode, the G.706 Annex B RAI bit, G706ANNBRAI, selects between two modes of operation concerning the transmission of RAI when the COMET is out of CRC-4 multiframe. When G706ANNBRAI is logic 1, the behaviour of RAI follows Annex B of G.706, i.e., RAI is transmitted only when out of basic frame, not when CRC-4-to-non-CRC-4 interworking is declared, nor when the offline framer is out of frame. When G706ANNBRAI is logic 0, the behaviour of RAI follows ETSI standards, i.e., RAI is transmitted when out
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PM4351 COMET
COMBINED E1/T1 TRANSCEIVER
of basic frame, when CRC-4-to-non-CRC-4 interworking is declared, and when the offline framer is out of frame. This bit only has effect in E1 mode. SIGAEN: The SIGAEN bit enables the operation of the signaling aligner (SIGA) to ensure superframe alignment of signaling bits between the backplane and the transmit DS-1 stream. When set to logic 1, the SIGA is inserted into the signaling bit data path before the T1-XBAS. When the signaling aligner is used, the backplane frame alignment indication must also be changed to indicate superframe alignment for the transmit backplane. When SIGAEN is set to logic 0, the SIGA is removed from the circuit. It is recommended that SIGAEN be set to logic 1 in T1 mode. This bit has no effect in E1 mode. OOCMFE0: When in E1 mode, the OOCMFE0 bit selects between two modes of operation concerning the transmission of E-bits when the COMET is out of CRC-4 multiframe. When OOCMFE0 is logic 0, the COMET transmits ones for the E-bits while out of CRC-4 multiframe. When OOCMFE0 is logic 1, the COMET transmits zeroes for the E-bits while out of CRC-4 multiframe. The option to transmit zeroes as E-bits while out of CRC-4 multiframe is provided to allow compliance with the CRC-4 to non-CRC-4 interworking procedure in Annex B of G.706. This bit only has effect in E1 mode. FDIS: The FDIS bit allows the framing generation through the transmitter to be disabled and the transmit data to pass through the transmitter unchanged. When FDIS is set to logic 1, the transmitter is disabled from generating framing. When FDIS is set to logic 0, the transmitter is enabled to generate and insert the framing into the transmit data. FBITBYP: The FBITBYP bit allows the frame synchronization bit in the input data stream, BTPCM, to bypass the generation through the XBAS and be reinserted into the appropriate position in the digital output stream. When FBITBYP is set to logic 1, the input frame synchronization bit is re-inserted into the output data stream. When FBITBYP is set to logic 0, the XBAS is allowed to generate the output frame synchronization bits.
PROPRIETARY AND CONFIDENTIAL
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PM4351 COMET
COMBINED E1/T1 TRANSCEIVER
This bit must be set to logic 0 when not in T1 ESF mode. CRCBYP: In T1 mode, when the CRCBYP bit is a logic 1, the framing bit corresponding to the CRC-6 bit position in the input data stream, BTPCM, passes transparently to the transmit output data stream. When CRCBYP is set to logic 0, the XBAS is allowed to generate the output CRC-6 bits. This bit must be set to logic 0 when not in T1 ESF mode. FDLBYP: In T1 mode, when the FDLBYP bit is a logic 1, the framing bit corresponding to the facility data link bit position in the input data stream, BTPCM, passes transparently to the transmit output data stream. When FDLBYP is set to logic 0, the XBAS is allowed to generate the output facility data link. This bit must be set to logic 0 when not in T1 ESF mode.
PROPRIETARY AND CONFIDENTIAL
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STANDARD PRODUCT DATA SHEET PMC-1970624 ISSUE 10
PM4351 COMET
COMBINED E1/T1 TRANSCEIVER
Register 006H: Transmit Timing Options Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W R/W R/W R/W R/W
Unused Unused OCLKSEL1 OCLKSEL0 PLLREF1 PLLREF0 Unused TXELSTBYP
X X 0 0 0 0 X 1
This register allows software to configure the options of the transmit timing section. TXELSTBYP: The TXELSTBYP bit allows the Transmit Elastic Store (TX-ELST) to be bypassed, eliminating the one frame delay incurred through the TX-ELST. When set to logic 1, the received data and clock inputs to TX-ELST are internally routed directly to the TX-ELST outputs. OCLKSEL1, OCLKSEL0: The OCLKSEL[1:0] bits select the source of the Transmit Jitter Attenuator FIFO output clock signal.
Table 17 - TJAT FIFO Output Clock Source OCLKSEL0 Source of FIFO Output Clock
OCLKSEL1
0
0
The TJAT FIFO output clock is driven with the internal jitter-attenuated 1.544 MHz or 2.048 MHz clock. The TJAT FIFO output clock is driven with the TCLKI input clock. In this mode, PLLREF[1:0] must be programmed to `b11.
0
1
PROPRIETARY AND CONFIDENTIAL
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PM4351 COMET
COMBINED E1/T1 TRANSCEIVER
OCLKSEL1
OCLKSEL0 Source of FIFO Output Clock
1
X
The TJAT FIFO output clock is driven with the FIFO input clock. In this mode the jitter attenuation is disabled and the input clock must be jitter-free. In this mode, PLLREF[1:0] must be programmed to `b00.
PLLREF1, PLLREF0: The PLLREF[1:0] bits select the source of the Transmit Jitter Attenuator phase locked loop reference signal as follows:
Table 18 PLLREF1 - TJAT PLL Source PLLREF0 Source of PLL Reference
0
0
TJAT FIFO input clock (either the conditioned BTCLK or the receive recovered clock, as selected by LINELB, assuming the TX-ELST is bypassed) conditioned BTCLK input (assuming the TX-ELST is bypassed) Receive recovered clock TCLKI input
0 1 1
1 0 1
If the BTCLK is configured as an output (CMODE bit of the Transmit Backplane Configuration register is a logic 0), only the recovered clock or the TCLKI input should be selected, or else the timing becomes self-referential and unpredictable. The following table illustrates the required bit settings for these various clock sources to affect the transmitted data:
Table 19 - Transmit Timing Options Summary
Bit Settings OCLKSEL1=0 OCLKSEL0=0 PLLREF1=0 PLLREF0=X LINELB=0 TXELSTBYP=1 Effect on Output Transmit Data Jitter attenuated. TCLKO is a smooth 1.544 MHz or 2.048 MHz. TCLKO referenced to BTCLK input. TX-ELST bypassed.
Input Transmit Data Synchronous to BTCLK input. Transmit Backplane Configuration register CMODE =1.
PROPRIETARY AND CONFIDENTIAL
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PM4351 COMET
COMBINED E1/T1 TRANSCEIVER
Input Transmit Data Synchronous to BTCLK output. Transmit Backplane Configuration register CMODE =0.
Bit Settings OCLKSEL1=0 OCLKSEL0=0 PLLREF1=1 PLLREF0=0 LINELB=0 TXELSTBYP=1
Effect on Output Transmit Data Jitter attenuated looptiming. TCLKO is a smooth 1.544 MHz or 2.048 MHz. Loop timed to the receive recovered clock. TX-ELST bypassed.
Synchronous to BTCLK input. Transmit Backplane Configuration register CMODE =1.
OCLKSEL1=0 OCLKSEL0=0 PLLREF1=1 PLLREF0=0 LINELB=0 TXELSTBYP=0
Jitter attenuated looptiming. TCLKO is a smooth 1.544 MHz or 2.048 MHz. Loop timed to the receive recovered clock. TX-ELST allows BTCLK to be plesiochronous.
Synchronous to BTCLK output. Transmit Backplane Configuration register CMODE =0.
OCLKSEL1=0 OCLKSEL0=0 PLLREF1=1 PLLREF0=1 LINELB=0 TXELSTBYP=1
Jitter attenuated. TCLKO is a smooth 1.544 MHz or 2.048 MHz. TCLKO and BTCLK referenced to TCLKI input. TX-ELST bypassed.
Synchronous to BTCLK input. Transmit Backplane Configuration register CMODE =1.
OCLKSEL1=0 OCLKSEL0=0 PLLREF1=1 PLLREF0=1 LINELB=0 TXELSTBYP=0
Jitter attenuated. TCLKO is a smooth 1.544 MHz or 2.048 MHz. TCLKO referenced to TCLKI input. TXELST allows BTCLK to be plesiochronous.
Synchronous to BTCLK input. Transmit Backplane Configuration register CMODE =1.
OCLKSEL1=1 OCLKSEL0=X PLLREF1=1 PLLREF0=1 LINELB=0 TXELSTBYP=1
No jitter attenuation. TCLKO is equivalent to BTCLK. TX-ELST bypassed.
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PM4351 COMET
COMBINED E1/T1 TRANSCEIVER
Input Transmit Data Synchronous to BTCLK output. Transmit Backplane Configuration register CMODE =0.
Bit Settings OCLKSEL1=0 OCLKSEL0=1 PLLREF1=1 PLLREF0=1 LINELB=0 TXELSTBYP=1
Effect on Output Transmit Data No jitter attenuation. TCLKO is equal to TCLKI (useful for higher rate MUX applications). The BTCLK output referenced to TCLKI. TX-ELST bypassed.
Synchronous to BTCLK input. Transmit Backplane Configuration register CMODE =1.
OCLKSEL1=0 OCLKSEL0=1 PLLREF1=1 PLLREF0=1 LINELB=0 TXELSTBYP=0
No jitter attenuation. TCLKO is equal to TCLKI (useful for higher rate MUX applications). TX-ELST allows BTCLK to be plesiochronous.
Transmit data ignored. Receive data is looped back.
OCLKSEL1=0 OCLKSEL0=0 PLLREF1=X PLLREF0=0 LINELB=1 TXELSTBYP=X
Line loopback with jitter attenuation.
Upon reset of the COMET, these bits are cleared to zero, selecting jitter attenuation with TCLKO referenced to the backplane transmit clock, BTCLK. Figure 12 illustrates the various bit setting options, with the reset condition highlighted. When TUNI is logic 0, PLLREF[1:0] must be configured such that the internal 24x clock references the Transmit line clock.
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PM4351 COMET
COMBINED E1/T1 TRANSCEIVER
Figure 12
- Transmit Timing Options
TX ELST
0 TXELSTBY P 0 1 1
LINELB FIFO input data clock Transmit line clock, TCLKO (becomes BTCLK output w hen CMODE=0)
BTCLK (input)
Optional freq. division and gapping
TJAT FIFO
FIFO output data clock
OCLKSEL1
Internal 24x clock
0 1
OCLKSEL0
1 00 01
PLLREF[1:0] Receive recovered clock "Jitter-free" line rate clock (1.544MHz or 2.048MHz)
0
TJAT PLL
10 11
TCLKI
PROPRIETARY AND CONFIDENTIAL
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PM4351 COMET
COMBINED E1/T1 TRANSCEIVER
Register 007H: Interrupt Source #1 Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
R R R R R R R R
PMON PRGD FRMR SIGX APRM TJAT RJAT CDRC
0 0 0 0 0 0 0 0
This register allows software to determine the block which produced the interrupt on the INTB output pin. Reading this register does not remove the interrupt indication; the corresponding block's interrupt status register must be read to remove the interrupt indication.
PROPRIETARY AND CONFIDENTIAL
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STANDARD PRODUCT DATA SHEET PMC-1970624 ISSUE 10
PM4351 COMET
COMBINED E1/T1 TRANSCEIVER
Register 008H: Interrupt Source #2 Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
R R R R R R R R
RX-ELST RDLC #3 RDLC #2 RDLC #1 TX-ELST TDPR #3 TDPR #2 TDPR #1
0 0 0 0 0 0 0 0
This register allows software to determine the block that produced the interrupt on the INTB output pin. Reading this register does not remove the interrupt indication; the corresponding block's interrupt status register must be read to remove the interrupt indication.
PROPRIETARY AND CONFIDENTIAL
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STANDARD PRODUCT DATA SHEET PMC-1970624 ISSUE 10
PM4351 COMET
COMBINED E1/T1 TRANSCEIVER
Register 009H: Interrupt Source #3 Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
R R R R R R R R
IBCD PDVD RBOC XPDE ALMI TRAN RLPS BTIF
0 0 0 0 0 0 0 0
This register allows software to determine the block that produced the interrupt on the INTB output pin. Reading this register does not remove the interrupt indication; the corresponding block's interrupt status register must be read to remove the interrupt indication.
PROPRIETARY AND CONFIDENTIAL
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STANDARD PRODUCT DATA SHEET PMC-1970624 ISSUE 10
PM4351 COMET
COMBINED E1/T1 TRANSCEIVER
Register 00AH: Master Diagnostics Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ID[5]: R R/W R/W R/W R/W R/W R/W
Unused ID[5] PAYLB LINELB RAIS DDLB TXMFP TXLOS
X 1 0 0 0 0 0 0
The ID[5] bit was added for COMET Rev G. In prior revisions, this bit was unused and defaulted to X. Please see the Register 00DH: Revision/Chip ID/Global PMON Update description for how to distinguish between COMET Rev F and G in software. PAYLB: The PAYLB bit selects the payload loopback mode, where the received data output from the RX-ELST is internally connected to the transmit data input of the transmitter. The data read out of RX-ELST is timed to the transmitter clock, and the transmit frame alignment is used to synchronize the output frame alignment of RX-ELST. The transmit frame alignment is either arbitrary (when the TX-ELST is used) or is specified by the BTFP input (when the TXELST is bypassed). During payload loopback, the data on BRPCM is only valid when the COMET is configured as a BRCLK master, BRFP master and the RX-ELST is bypassed. When the RX-ELST is not bypassed, the BRPCM output is forced to all-ones. When PAYLB is set to logic 1, the payload loopback mode is enabled. When PAYLB is set to logic 0, the loopback mode is disabled. In T1 mode, if the TDPR #1 is configured to send performance reports from the T1-APRM, this bit requires two updating cycles before being included in the performance report. Only one of PAYLB, LINELB, and DDLB can be enabled at any one time. LINELB: The LINELB bit selects the line loopback mode, where the recovered data are internally directed to the digital inputs of the transmit jitter attenuator. In analog mode (RUNI is logic 0), the data sent to the TJAT is the recovered
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PM4351 COMET
COMBINED E1/T1 TRANSCEIVER
data from the output of the CDRC block. In digital mode (RUNI is logic 1), the data sent to the TJAT is a sampled version of the RDAT digital input. When LINELB is set to logic 1, the line loopback mode is enabled. When LINELB is set to logic 0, the line loopback mode is disabled. Note that when line loopback is enabled, to correctly attenuate the jitter on the receive clock, the contents of the TJAT Reference Clock Divisor and Output Clock Divisor registers should be programmed to 2FH in T1 or FFH in E1 and the Transmit Timing Options register should be cleared to all zeros. Only one of PAYLB, LINELB, and DDLB can be enabled at any one time. RAIS: When a logic 1, the RAIS bit forces all ones into the BRPCM data stream. The BRSIG data stream will freeze at the current valid signaling. This capability is provided to indicate the unavailability of the line when line loopback is active. DDLB: The DDLB bit selects the diagnostic digital loopback mode, where the COMET is configured to internally direct the output of the TJAT to the inputs of the receiver section. In analog mode (RUNI is logic 0), the dual-rail RZ outputs of the TJAT are directed to the dual-rail inputs of the CDRC. In digital mode (RUNI is logic 1), the single-rail NRZ outputs of the TJAT are directed to the inputs of the RJAT. When DDLB is set to logic 1, the diagnostic digital loopback mode is enabled. When DDLB is set to logic 0, the diagnostic digital loopback mode is disabled. When configured for diagnostic digital loopback, the TUNI and RUNI bits must be set to the same value. Only one of PAYLB, LINELB, and DDLB can be enabled at any one time. TXMFP: In T1 mode, the TXMFP bit introduces a mimic framing pattern in the digital output of the basic transmitter by forcing a copy of the current framing bit into bit location 1 of the frame, thereby creating a mimic pattern in the bit position immediately following the correct framing bit. When TXMFP is set to logic 1, the mimic framing pattern is generated. When TXMFP is set to logic 0, no mimic pattern is generated. TXLOS: The TXLOS bit provides a method of suppressing the output of the transmitter in T1 digital mode. When TXLOS is set to logic 1, the E1/T1B bit in the Global Configuration register is a logic 0 and the TUNI bit in the Transmit Line Interface Configuration register is a logic 1, the transmit output, TDAT is forced to all-zeros. In both E1 and T1 analog mode (TUNI is logic 0), the TXTIP and TXRING outputs can be forced to all-zeros by programming the XLPG Line Driver Configuration register.
PROPRIETARY AND CONFIDENTIAL
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STANDARD PRODUCT DATA SHEET PMC-1970624 ISSUE 10
PM4351 COMET
COMBINED E1/T1 TRANSCEIVER
Register 00BH: Master Test Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 W W W W R/W W R/W
Unused IDDQEN PMCATST PMCTST DBCTRL IOTST HIZDATA HIZIO
X X X X 0 0 0 0
This register is used to select COMET test features. All bits, except for PMCTST, PMCATST and IDDQEN are reset to zero by a hardware reset of the COMET; a software reset of the COMET does not affect the state of the bits in this register. Refer to the Test Features Description section for more information. IDDQEN: The IDDQEN bit is used to configure the COMET for IDDQ tests. IDDQEN is cleared when CSB is high and RSTB is low or when IDDQEN is written as logic 0. When the IDDQEN bit is set to logic 1, the HIGHZ bit in the XLPG Line Driver Configuration register must also be set to logic 1. PMCATST: The PMCATST bit is used to configure the analog portion of the COMET for PMC's manufacturing tests. PMCATST is cleared when CSB is high and RSTB is low or when PMCATST is written as logic 0. PMCTST: The PMCTST bit is used to configure the COMET for PMC's manufacturing tests. When PMCTST is set to logic 1, the COMET microprocessor port becomes the test access port used to run the PMC manufacturing test vectors. The PMCTST bit is logically "ORed" with the IOTST bit, and is cleared by setting CSB high. DBCTRL: The DBCTRL bit is used to pass control of the data bus drivers to the CSB pin. When the DBCTRL bit is set to logic 1, the CSB pin controls the output
PROPRIETARY AND CONFIDENTIAL
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PM4351 COMET
COMBINED E1/T1 TRANSCEIVER
enable for the data bus. While the DBCTRL bit is set, holding the CSB pin high causes the COMET to drive the data bus and holding the CSB pin low tri-states the data bus. The DBCTRL bit overrides the HIZDATA bit. The DBCTRL bit only has effect when the IOTST or PMCTST bit is set to logic 1. The DBCTRL bit is used to measure the drive capability of the data bus driver pads. IOTST: The IOTST bit is used to allow normal microprocessor access to the test registers and control the test mode in each block in the COMET for board level testing. When IOTST is a logic 1, all blocks are held in test mode and the microprocessor may write to a block's test mode 0 registers to manipulate the outputs of the block and consequently the device outputs (refer to the "Test Mode 0 Details" in the "Test Features" section). HIZIO, HIZDATA: The HIZIO and HIZDATA bits control the tri-state modes of the COMET . While the HIZIO bit is a logic 1, all output pins of the COMET except the data bus are held in a high-impedance state. The microprocessor interface is still active. While the HIZDATA bit is a logic 1, the data bus is also held in a highimpedance state which inhibits microprocessor read cycles.
PROPRIETARY AND CONFIDENTIAL
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PM4351 COMET
COMBINED E1/T1 TRANSCEIVER
Register 00CH: Analog Diagnostics Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W R/W R/W R/W
Unused Unused Reserved Reserved Unused Unused Reserved Reserved
X X 0 0 X X 0 0
Reserved: These bits must be a logic 0 for correct operation.
PROPRIETARY AND CONFIDENTIAL
102
STANDARD PRODUCT DATA SHEET PMC-1970624 ISSUE 10
PM4351 COMET
COMBINED E1/T1 TRANSCEIVER
Register 00DH: Revision/Chip ID/Global PMON Update Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
R R R R R R R R
TYPE[2] TYPE[1] TYPE[0] ID[4] ID[3] ID[2] ID[1] ID[0]
0 0 1 0 0 1 0 1
The version identification bits, ID[4:0], are set to a fixed value representing the version number of the COMET. For COMET Rev G, ID[5] was added to the Master Diagnostics register (address 00AH). In order to uniquely identify Rev G in software, the following routine can be executed: i. Read Register 00DH: Revision/Chip ID/Global PMON Update. Revision F or Revision G will contain "00100101". ii. Read Register 00AH: Master Diagnostics. In Revision F, bit 6 will read logic 0, as this is the value charged on the bus-holder due to the last read. In Revision G, bit 6 will read logic 1, as this is the value driven by the new ID[5] bit. NOTE: For this two step sequence to work, step (ii) must follow immediately after step (i) without any intervening microprocessor accesses. Any intervening accesses could change the value charged onto the bit 6 bus-holder, invalidating step (ii). Writing any value to this register causes all performance monitor counters to be updated simultaneously. The chip identification bits, TYPE[2:0], are set to "001" representing the COMET.
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Register 00EH: Reset Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 RESET: R/W
Unused Unused Unused Unused Unused Unused Unused RESET
X X X X X X X 0
The RESET bit implements a software reset. If the RESET bit is a logic 1, the COMET is held in reset. This bit is not self-clearing; therefore, a logic 0 must be written to bring the COMET out of reset. Holding the COMET in a reset state effectively puts it into a low-power, stand-by mode. A hardware reset clears the RESET bit, thus deasserting the software reset.
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Register 00FH: PRGD Positioning/Control and HDLC Control Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
R/W R/W R/W R/W R/W R/W R/W R/W
HDLC3_DIS HDLC2_DIS HDLC1_DIS Nx56k_GEN Nx56k_DET RXPATGEN UNF_GEN UNF_DET
0 0 0 0 0 0 0 0
This register modifies the way in which the PRGD is used by the TPSC and RPSC. More information on using PRGD is available in the Operation section. HDLC3_DIS: The HDLC3_DIS bit, when set to logic 1, is used to disable the clock to the TDPR #3 and RDLC #3, putting them into a low power, stand-by mode. When the HDLC3_DIS bit is set to logic 0, the clock to the TDPR #3 and RDLC #3 is enabled. HDLC2_DIS: The HDLC2_DIS bit, when set to logic 1, is used to disable the clock to the TDPR #2 and RDLC #2, putting them into a low power, stand-by mode. When the HDLC2_DIS bit is set to logic 0, the clock to the TDPR #2 and RDLC #2 is enabled. HDLC1_DIS: The HDLC1_DIS bit, when set to logic 1, is used to disable the clock to the TDPR #1 and RDLC #1, putting them into a low power, stand-by mode. When the HDLC1_DIS bit is set to logic 0, the clock to the TDPR #1 and RDLC #1 is enabled. Nx56k_GEN: The Nx56k_GEN bit is active when the RPSC or TPSC is used to insert PRBS into selected DS0 channels of the transmit or receive stream. When the Nx56kbps generation bit is set to logic 1, the pattern is only inserted in the first 7 bits of the selected DS0 channels, and gapped on the eighth bit. This
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is particularly useful when using the jammed-bit-8 zero code suppression in the transmit direction, for instance when sending a Nx56kbps fractional T1/E1 loopback sequence. This bit has no effect when UNF_GEN is set to logic 1. Nx56k_DET: The Nx56k_DET bit is active when the RPSC or TPSC is used to detect PRBS in selected DS0 channels of the transmit or receive stream. When the Nx56kbps detection bit is set to logic 1, the pattern generator only looks at the first 7 bits of the selected DS0 channels, and gaps out the eighth bit. This is particularly useful when searching for fractional T1 loopback codes in an Nx56kbps fractional T1 signal. This bit has no effect when UNF_DET is set to logic 1. RXPATGEN: The Receive Pattern Generate (RXPATGEN) bit controls the location of the pattern generator/detector. When RXPATGEN is set to logic 1, the pattern generator is inserted in the receive path and the pattern detector is inserted in the transmit path. Timeslots from the receive line may be overwritten with generated patterns before appearing on the receive backplane interface, and timeslots from the transmit backplane interface may be checked for the generated pattern before appearing on the transmit line. When RXPATGEN is set to logic 0, the pattern detector is inserted in the receive path and the pattern generator is inserted in the transmit path. Timeslots from the transmit backplane interface may be overwritten with generated patterns before appearing on the transmit line, and timeslots from the receive line may be checked for the generated pattern before appearing on the receive backplane interface. UNF_GEN When the Unframed Pattern Generation bit (UNF_GEN) is set to logic 1, the PRGD will overwrite all 193 bits/256 bits in every frame in the direction specified by the RXPATGEN bit. If the generator is enabled in the transmit path, unless signaling and/or framing is disabled, the transmitter will still overwrite the signaling bit positions and/or the framing bit position. Similarly, if pattern generation is enabled in the receive direction, the pattern will overwrite the framing bit positions. The UNF_GEN bit overrides any pertimeslot pattern generation specified in the TPSC or RPSC. When RXPATGEN = 0, UNF_GEN also overrides idle code insertion and data inversion in the transmit direction, just like the TEST bit in the TPSC. UNF_DET When the Unframed Pattern Detection bit (UNF_DET) is set to logic 1, the PRGD will search for the pattern in all 193 bits/256 bits of the transmit or
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receive stream, depending on the setting of RXPATGEN. The UNF_DET bit overrides any per-timeslot pattern detection specified in the TPSC or RPSC.
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Register 010H: CDRC Configuration Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
R/W R/W R/W R/W R/W R/W R/W R/W
AMI LOS[1] LOS[0] Reserved Reserved ALGSEL O162 Reserved
0 0 0 0 0 0 0 0
When the RUNI bit of the Receive Line Interface Configuration register is a logic 1, this register is held reset. Reserved: These bits must be a logic 0 for correct operation. O162: If the AMI bit is logic 0 in E1 mode, the Recommendation O.162 compatibility select bit (O162) allows selection between two line code violation definitions: If O162 is a logic 0, a line code violation is indicated if the serial stream does not match the verbatim HDB3 definition given in Recommendation G.703. A bipolar violation that is not part of an HDB3 signature or a bipolar violation in an HDB3 signature that is the same polarity as the last bipolar violation results in a line code violation indication. If O162 is a logic 1, a line code violation is indicated if a bipolar violation is of the same polarity as the last bipolar violation, as per Recommendation O.162. The O162 bit has no effect in T1 mode. ALGSEL: The Algorithm Select (ALGSEL) bit specifies the algorithm used by the DPLL for clock and data recovery. The choice of algorithm determines the high frequency input jitter tolerance of the CDRC. When ALGSEL is set to logic 1, the CDRC jitter tolerance is increased to approach 0.5 UIpp for jitter
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frequencies above 20 kHz. When ALGSEL is set to logic 0, the jitter tolerance is increased for frequencies below 20 kHz (i.e. the tolerance is improved by 20% over that of ALGSEL=1 at these frequencies), but the tolerance approaches 0.4 UIpp at the higher frequencies. AMI: The alternate mark inversion (AMI) bit specifies the line coding of the incoming signal. A logic 1 selects AMI line coding by disabling HDB3 decoding if E1 mode and B8ZS in T1 mode. In E1 mode, a logic 0 selects HDB3 line decoding which entails substituting an HDB3 signature with four zeros. In T1 mode, a logic 0 selects B8ZS line decoding which entails substituting an B8ZS signature with eight zeros. LOS[1:0]: The loss of signal threshold is set by the operating mode and the state of the AMI, LOS[1] and LOS[0] bits:
Table 20 Mode - Loss of Signal Thresholds AMI LOS[1] LOS[0] Threshold (PCM periods)
E1 T1 X X X X
0 0 1 X X X
0 0 0 0 1 1
0 0 0 1 0 1
10 15 15 31 63 175
When the number of consecutive zeros on the incoming PCM line exceeds the programmed threshold, the LOSV status bit is set. For example, if the threshold is set to 10, the 11th zero causes the LOSV bit to be set. The LOSV bit clears when a pulse occurs.
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Register 011H: CDRC Interrupt Control Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
R/W R/W R/W R/W
LCVE LOSE LCSDE ZNDE Unused Unused Unused Unused
0 0 0 0 X X X X
When the RUNI bit of the Receive Line Interface Configuration register is a logic 1, this register is held reset. The bit positions LCVE, LOSE, LCSDE and ZNDE (bits 7 to 4) of this register are interrupt enables to select which of the status events (Line Code Violation , Loss Of Signal, HDB3 signature, B8ZS signature or N Zeros), either singly or in combination, are enabled to generate an interrupt on the microprocessor INTB pin when they are detected. A logic 1 bit in the corresponding bit position enables the detection of these signals to generate an interrupt; a logic 0 bit in the corresponding bit position disables that signal from generating an interrupt. When the COMET is reset, LCVE, LOSE, LCSDE and ZNDE are set to logic 0, disabling these events from generating an interrupt.
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Register 012H: CDRC Interrupt Status Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
R R R R
LCVI LOSI LCSDI ZNDI Unused Unused Unused
X X X X X X X X
R
LOSV
When the RUNI bit of the Receive Line Interface Configuration register is a logic 1, this register is held reset. The ZNDI, LCSDI, LOSI and LCVI (bits 4 to 7) of this register indicate which of the status events have occurred since the last time this register was read. A logic 1 in any of these bit positions indicates that the corresponding event was detected. Bits ZNDI, LCSDI, LOSI and LCVI are cleared to logic 0 by reading this register. LOSV: The LOSV bit reflects the status of the LOS alarm. ZNDI: The consecutive zeros detection interrupt (ZNDI) indicates that N consecutive spaces have occurred, where N is four for E1 and eight for T1. This bit can be used to detect an AMI coded signal. LCSDI: The line code signature detection interrupt (LCSDI) indicates that a valid line code signature has occurred. In T1 mode, the B8ZS signature is defined as 000+-0-+ if the previous impulse is positive, or 000-+0+- if it is negative. In E1 mode, a valid HDB3 signature is defined as a bipolar violation preceded by two zeros. This bit can be used to detect an HDB3 coded signal in E1 mode and B8ZS coded signal in T1.
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LOSI: The LOSI bit is set to a logic 1 when the LOSV bit changes state. LCVI: The line code violation interrupt (LCVI) indicates a series of marks and spaces has occurred in contradiction to the defined line code (AMI, B8ZS or HDB3).
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Register 013H: Alternate Loss of Signal Status Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
R/W R
ALTLOSE ALTLOSI Unused Unused Unused Unused Unused
0 X X X X X X X
R
ALTLOS
This register is only operational when the RUNI bit of the Receive Line Interface Configuration register is a logic 0. The alternate loss of signal status provides a more stringent criteria for the deassertion of the alarm than the LOS indication in the CDRC Interrupt Status register. ALTLOSE: If the ALTLOSE bit is a logic 1, the INTB output is asserted low when the ALTLOS status bit changes state. ALTLOSI: The ALTLOSI bit is set high when the ALTLOS status bit changes state. It is cleared when this register is read. ALTLOS: The ALTLOS bit is asserted upon the absence of marks for the threshold of bit periods specified by the LOS[1:0] register bits. The ALTLOS bit is deasserted only after pulse density requirements have been met. In T1 mode, there must be N ones in each and every time window of 8(N+1) data bits (where N can equal 1 through 23). In E1 mode, ALTLOS is deasserted only after 255 bit periods during which no sequence of four zeros has been received.
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Register 014H: RJAT Interrupt Status Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 UNDI: R R
Unused Unused Unused Unused Unused Unused OVRI UNDI
X X X X X X X X
The UNDI bit is asserted when an attempt is made to read data from the receive FIFO when the FIFO is already empty. When UNDI is a logic 1, an underrun event has occurred. Reading this register will clear the UNDI bit to logic 0. OVRI: The OVRI bit is asserted when an attempt is made to write data into the receive FIFO when the FIFO is already full. When OVRI is a logic 1, an overrun event has occurred. Reading this register will clear the OVRI bit to logic 0.
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Register 015H: RJAT Divider N1 Control Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
R/W R/W R/W R/W R/W R/W R/W R/W
N1[7] N1[6] N1[5] N1[4] N1[3] N1[2] N1[1] N1[0]
0 0 1 0 1 1 1 1
This register contains an 8-bit binary number, N1, which is one less than the magnitude of the reference clock divisor. The reference divisor magnitude, (N1+1), is the ratio between the frequency of the recovered clock (or the transmit clock if a diagnostic loopback is enabled) and the frequency at the phase discriminator input. Writing to this register will reset the PLL. If the FIFORST bit of the RJAT Configuration register is set high, a write to this register will reset both the PLL and FIFO. The default value of N1 after a device reset is 47 = 2FH.
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Register 016H: RJAT Divider N2 Control Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
R/W R/W R/W R/W R/W R/W R/W R/W
N2[7] N2[6] N2[5] N2[4] N2[3] N2[2] N2[1] N2[0]
0 0 1 0 1 1 1 1
This register contains an 8-bit binary number, N2, which is one less than the magnitude of the output clock divisor. The output clock divisor magnitude, (N2+1), is the ratio between the frequency of the smooth output clock, BRCLK, and the frequency applied to the phase discriminator input. Writing to this register will reset the PLL. Writing to this register will reset the PLL. If the FIFORST bit of the RJAT Configuration register is set high, a write to this register will reset both the PLL and FIFO. The default value of N2 after a device reset is 47 = 2FH.
Recommendations
In general, the relationship N1 = N2 must always be true in order for the PLL to operate correctly. In order to meet jitter transfer specifications for some modes, such as basic E1 operation, N1 and N2 must be large in order to reduce the PLL transfer cutoff frequency. In general, for E1 operation, N2 is set to FFH to meet ETSI jitter transfer specifications. For T1 mode, the recommended values are N1 = N2 = 2FH. For E1 mode, the recommended values are N1 = N2 = FFH.
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Register 017H: RJAT Configuration Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 CENT: R/W R/W R/W R/W R/W
Unused Unused Unused CENT UNDE OVRE FIFORST LIMIT
X X X 0 0 0 0 1
The CENT bit allows the FIFO to self-center its read pointer, maintaining the pointer at least 4 UI away from the FIFO being empty or full. When CENT is set to logic 1, the FIFO is enabled to self-center for the next 384 transmit data bit period, and for the first 384 bit periods following an overrun or underrun event. If an EMPTY or FULL alarm occurs during this 384 UI period, the period will be extended by the number of UI that the EMPTY or FULL alarm persists. During the EMPTY or FULL alarm conditions, data is lost. When CENT is set to logic 0, the self-centering function is disabled, allowing the data to pass through uncorrupted during EMPTY or FULL alarm conditions. The recommended value of CENT is logic 1. UNDE: Setting the UNDE bit to logic 1 enables an underrun event to assert the INTB output low. OVRE: Setting the OVRE bit to logic 1 enables an overrun event to assert the INTB output low. FIFORST: Setting the FIFORST bit allows the FIFO to reset when the PLL is reset by software. When FIFORST is logic 1, writing to the PLL Divider Control Registers N1 and N2 will cause both the PLL and FIFO to reset. When
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FIFORST is logic 0, writing to the Divider Control Registers N1 and N2 will cause only the PLL to reset. LIMIT: Setting the LIMIT bit to logic 1 will limit the PLL jitter attenuation by enabling the FIFO to increase or decrease the frequency of the smooth output clock whenever the FIFO is within one UI of overflowing or underflowing. This limiting of jitter ensures that no data is lost during high phase shift conditions. When LIMIT is set to logic 0, underflows and overflows may occur. The recommended value of LIMIT is logic 0.
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Register 018H: TJAT Interrupt Status Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 UNDI: R R
Unused Unused Unused Unused Unused Unused OVRI UNDI
X X X X X X X X
The UNDI bit is asserted when an attempt is made to read data from the transmit FIFO when the FIFO is already empty. When UNDI is a logic 1, an underrun event has occurred. Reading this register will clear the UNDI bit to logic 0. OVRI: The OVRI bit is asserted when an attempt is made to write data into the transmit FIFO when the FIFO is already full. When OVRI is a logic 1, an overrun event has occurred. Reading this register will clear the OVRI bit to logic 0.
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Register 019H: TJAT Jitter Attenuator Divider N1 Control Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
R/W R/W R/W R/W R/W R/W R/W R/W
N1[7] N1[6] N1[5] N1[4] N1[3] N1[2] N1[1] N1[0]
0 0 1 0 1 1 1 1
This register contains an 8-bit binary number, N1, which is one less than the magnitude of the reference clock divisor. The reference divisor magnitude, (N1+1), is the ratio between the frequency of the reference clock (as selected by the PLLREF1 and PLLREF0 bits of the Transmit Timing Options register) and the frequency at the phase discriminator input. Writing to this register will reset the PLL. If the FIFORST bit of the TJAT Configuration register is set high, a write to this register will reset both the PLL and FIFO. The default value of N1 after a device reset is 47 = 2FH.
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Register 01AH: TJAT Divider N2 Control Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
R/W R/W R/W R/W R/W R/W R/W R/W
N2[7] N2[6] N2[5] N2[4] N2[3] N2[2] N2[1] N2[0]
0 0 1 0 1 1 1 1
This register contains an 8-bit binary number, N2, which is one less than the magnitude of the output clock divisor. The output clock divisor magnitude, (N2+1), is the ratio between the frequency of the smooth output clock and the frequency applied to the phase discriminator input. Writing to this register will reset the PLL. If the FIFORST bit of the TJAT Configuration register is set high, a write to this register will reset both the PLL and FIFO. The default value of N2 after a device reset is 47 = 2FH.
Recommendations
In general, the relationship Fref/(N1+1) = Fout/(N2+1) must always be true in order for the PLL to operate correctly. Minimizing the values of N1 and N2 while keeping the above equation true minimizes intrinsic jitter. However, the minimum valid value for N2 is 1FH. In order to meet jitter transfer specifications for some modes, such as basic E1 operation, N1 and N2 must be large in order to reduce the PLL transfer cutoff frequency. In general, for E1 operation, N2 is set to FFH to meet ETSI jitter transfer specifications. When dealing with extremely low frequency references, such as an 8kHz reference clock, the N1 and N2 should configured so that Fref/(N1+1) and Fout/(N2+1) are both 8kHz results. Thus, for an 8kHz reference, N1 is 00H.
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The table below summarizes the recommended values for N1 and N2 for common modes of operation.
PLL Reference, as set by register bits PLLREF[1:0] PLL Output Frequency N1[7:0] N2[7:0]
1.544 MHz 2.048 MHz 2.048 MHz 1.544 MHz nominal 1.544 MHz (derived from gapped 1 2.048 MHz) 8 kHz 16 kHz 8 kHz 16 kHz
1
1.544 MHz (T1) 2.048 MHz (E1) 1.544 MHz (T1) 2.048 MHz (E1) 1.544 MHz (T1)
2FH FFH FFH C0H C0H
2FH FFH C0H FFH C0H
1.544 MHz (T1) 1.544 MHz (T1) 2.048 MHz (E1) 2.048 MHz (E1)
00H 01H 00H 01H
C0H C0H FFH FFH
Nominal 1.544 MHz is derived from a gapped 2.048 MHz when in T1 mode with the BTIF's RATE[1:0] bits set to "01", "10", or "11" and BTCLK configured as the reference.
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Register 01BH: TJAT Configuration Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 CENT: R/W R/W R/W R/W R/W
Unused Unused Unused CENT UNDE OVRE FIFORST LIMIT
X X X 0 0 0 0 1
The CENT bit allows the FIFO to self-center its read pointer, maintaining the pointer at least 4 UI away from the FIFO being empty or full. When CENT is set to logic 1, the FIFO is enabled to self-center for the next 384 transmit data bit period, and for the first 384 bit periods following an overrun or underrun event. If an EMPTY or FULL alarm occurs during this 384 UI period, the period will be extended by the number of UI that the EMPTY or FULL alarm persists. During the EMPTY or FULL alarm conditions, data is lost. When CENT is set to logic 0, the self-centering function is disabled, allowing the data to pass through uncorrupted during EMPTY or FULL alarm conditions. The recommended value of CENT is logic 1. UNDE: Setting the UNDE bit to logic 1 enables an underrun event to assert the INTB output low. OVRE: Setting the OVRE bit to logic 1 enables an overrun event to assert the INTB output low. FIFORST: Setting the FIFORST bit allows the FIFO to reset when the PLL is reset by software. When FIFORST is logic 1, writing to the PLL Divider Control Registers N1 and N2 will cause both the PLL and FIFO to reset. When
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FIFORST is logic 0, writing to the Divider Control Registers N1 and N2 will cause only the PLL to reset. LIMIT: Setting the LIMIT bit to logic 1 will limit the PLL jitter attenuation by enabling the FIFO to increase or decrease the frequency of the smooth output clock whenever the FIFO is within one UI of overflowing or underflowing. This limiting of jitter ensures that no data is lost during high phase shift conditions. When LIMIT is set to logic 0, underflows and overflows may occur. The recommended value of LIMIT is logic 0.
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Register 01CH: RX-ELST Configuration Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reserved:
R/W
Reserved Unused Unused Unused Unused Unused
0 X X X X X 1 1
R/W R/W
IR OR
This bit must be a logic 0 for correct operation. IR: The IR bit selects the input frame format. The IR bit must be set to logic 1 for E1 mode; it must be logic 0 for T1 mode. OR: The OR bit selects the output frame format. The OR bit must be set to logic 1 for E1 mode; it must be logic 0 for T1 mode.
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Register 01DH: RX-ELST Interrupt Enable/Status Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SLIPE: R/W R R
Unused Unused Unused Unused Unused SLIPE SLIPD SLIPI
X X X X X 0 X X
The SLIPE bit position is an interrupt enable that when set, enables the INTB output to assert low when a slip occurs. When the block is reset the SLIPE bit position is cleared and interrupt generation is disabled. SLIPD: The SLIPD bit indicates the direction of the last slip. If the SLIPD bit is a logic 1 then the last slip was due to the frame buffer becoming full; a frame was deleted. If the SLIPD bit is a logic 0 then the last slip was due to the frame buffer becoming empty; a frame was duplicated. SLIPI: The SLIPI bit is set if a slip occurred since the last read of this register. The SLIPI bit is cleared upon reading this register.
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Register 01EH: RX-ELST Idle Code Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
R/W R/W R/W R/W R/W R/W R/W R/W
D7 D6 D5 D4 D3 D2 D1 D0
1 1 1 1 1 1 1 1
The contents of this register replace the timeslot data in the BRPCM serial data stream when the framer is out of frame and the TRKEN bit in the Receive Options register is a logic 1. Since the transmission of all ones timeslot data is a common requirement, this register is set to all ones on a reset condition. D7 is the first to be transmitted. The writing of the idle code pattern is asynchronous with respect to the output data clock. One timeslot of idle code data will be corrupted if the register is written to when the framer is out of frame.
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Register 020H: TX-ELST Configuration Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reserved:
R/W
Reserved Unused Unused Unused Unused Unused
0 X X X X X 1 1
R/W R/W
IR OR
This bit must be programmed to logic 0 for correct operation. IR: The IR bit selects the input frame format. The IR bit must be set to logic 1 for E1 mode; it must be logic 0 for T1 mode. OR: The OR bit selects the output frame format. The OR bit must be set to logic 1 for E1 mode; it must be logic 0 for T1 mode.
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Register 021H: TX-ELST Interrupt Enable/Status Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SLIPE: R/W R R
Unused Unused Unused Unused Unused SLIPE SLIPD SLIPI
X X X X X 0 X X
The SLIPE bit position is an interrupt enable that when set, enables the INTB output to assert low when a slip occurs. When the block is reset the SLIPE bit position is cleared and interrupt generation is disabled. SLIPD: The SLIPD bit indicates the direction of the last slip. If the SLIPD bit is a logic 1 then the last slip was due to the frame buffer becoming full; a frame was deleted. If the SLIPD bit is a logic 0 then the last slip was due to the frame buffer becoming empty; a frame was duplicated. SLIPI: The SLIPI bit is set if a slip occurred since the last read of this register. The SLIPI bit is cleared upon reading this register.
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Register 028H: RXCE Receive Data Link 1 Control Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
R/W R/W R/W R/W R/W R/W R/W R/W
DL1_EVEN DL1_ODD T1_DL_EN DL1_TS[4] DL1_TS[3] DL1_TS[2] DL1_TS[1] DL1_TS[0]
0 0 1 0 0 0 0 0
This register, along with the RXCE Data Link 1 Bit Select register, controls the extraction of the data link terminated by RDLC #1. Refer to the "Using the Internal HDLC Receivers" description in the Operation section for details on terminating HDLC frames. DL1_EVEN: The data link 1 even select (DL1_EVEN) bit controls whether or not the first data link is extracted from the even frames of the receive data stream. If DL1_EVEN is a logic 0, the data link is not extracted from the even frames. If DL1_EVEN is a logic 1, the data link is extracted from the even frames. In E1 mode, the frames in an E1 CRC-4 multiframe are considered to be numbered from 0 to 15; in T1 mode, the frames in a superframe are considered to be numbered from 1 to 12 (or 1 to 24 in an extended superframe). DL1_ODD: The data link 1 odd select (DL1_ODD) bit controls whether or not the first data link is extracted from the odd frames of the receive data stream. If DL1_ODD is a logic 0, the data link is not extracted from the odd frames. If DL1_ODD is a logic 1, the data link is extracted from the odd frames. T1_DL_EN: The T1 data link enable bit allows the termination of the ESF or T1DM data links when in T1 mode. If T1_DL_EN is a logic 1, the ESF, FMS1 and FMS0 bits of the T1 FRMR Configuration register determine the bit locations from which the data link is extracted. When the T1_DL_EN bit is a logic 1, the DL1_EVEN and DL1_ODD bits must both be set to logic 0. This bit must be set to logic 0 when in E1 mode.
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DL1_TS[4:0]: The data link 1 time slot (DL1_TS[4:0]) bits gives a binary representation of the time slot/channel from which the data link is to be extracted. Note that T1 channels 1 to 24 are mapped to values 0 to 23. The DL1_TS[4:0] bits have no effect when DL1_EVEN and DL1_ODD are both a logic 0.
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Register 029H: RXCE Receive Data Link 1 Bit Select Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
R/W R/W R/W R/W R/W R/W R/W R/W
DL1_BIT[7] DL1_BIT[6] DL1_BIT[5] DL1_BIT[4] DL1_BIT[3] DL1_BIT[2] DL1_BIT[1] DL1_BIT[0]
0 0 0 0 0 0 0 0
DL1_BIT[7:0]: The data link 1 bit select (DL1_BIT[7:0]) bits controls which bits of the time slot/channel are to be extracted and passed to RDLC #1. If DL1_BIT[x] is a logic 1, that bit is extracted as part of the data link. To extract the data link from the entire time slot, all eight DL1_BIT[x] bits must be set to a logic 1. DL1_BIT[7] corresponds to the most significant bit (bit 1, the first bit received) of the time slot and DL1_BIT[0] corresponds to the least significant bit (bit 8, the last bit received) of the time slot. The DL1_BIT[7:0] bits have no effect when the DL1_EVEN and DL1_ODD bits of the RXCE Data Link 1 Control register are both logic 0.
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Register 02AH: RXCE Receive Data Link 2 Control Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
R/W R/W R/W R/W R/W R/W R/W R/W
DL2_EVEN DL2_ODD Unused DL2_TS[4] DL2_TS[3] DL2_TS[2] DL2_TS[1] DL2_TS[0]
0 0 X 0 0 0 0 0
This register, along with the RXCE Data Link 2 Bit Select register, controls the extraction of the data link terminated by RDLC #2. Refer to the "Using the Internal HDLC Receivers" description in the Operation section for details on terminating HDLC frames. DL2_EVEN: The data link 2 even select (DL2_EVEN) bit controls whether or not the second data link is extracted from the even frames of the receive data stream. If DL2_EVEN is a logic 0, the data link is not extracted from the even frames. If DL2_EVEN is a logic 1, the data link is extracted from the even frames. In E1 mode, the frames in an E1 CRC-4 multiframe are considered to be numbered from 0 to 15; in T1 mode, the frames in a superframe are considered to be numbered from 1 to 12 (or 1 to 24 in an extended superframe). DL2_ODD: The data link 2 odd select (DL2_ODD) bit controls whether or not the second data link is extracted from the odd frames of the receive data stream. If DL2_ODD is a logic 0, the data link is not extracted from the odd frames. If DL2_ODD is a logic 1, the data link is extracted from the odd frames. DL2_TS[4:0]: The data link 2 time slot (DL2_TS[4:0]) bits gives a binary representation of the time slot/channel from which the data link is to be extracted. Note that T1 channels 1 to 24 are mapped to values 0 to 23. The DL2_TS[4:0] bits have no effect when DL2_EVEN and DL2_ODD are both a logic 0.
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Register 02BH: RXCE Receive Data Link 2 Bit Select Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
R/W R/W R/W R/W R/W R/W R/W R/W
DL2_BIT[7] DL2_BIT[6] DL2_BIT[5] DL2_BIT[4] DL2_BIT[3] DL2_BIT[2] DL2_BIT[1] DL2_BIT[0]
0 0 0 0 0 0 0 0
DL2_BIT[7:0]: The data link 2 bit select (DL2_BIT[7:0]) bits controls which bits of the time slot/channel are to be extracted and passed to RDLC #2. If DL2_BIT[x] is a logic 1, that bit is extracted as part of the data link. To extract the data link from the entire time slot, all eight DL2_BIT[x] bits must be set to a logic 1. DL2_BIT[7] corresponds to the most significant bit (bit 1, the first bit received) of the time slot and DL2_BIT[0] corresponds to the least significant bit (bit 8, the last bit received) of the time slot. The DL2_BIT[7:0] bits have no effect when the DL2_EVEN and DL2_ODD bits of the RXCE Data Link 2 Control register are both logic 0.
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Register 02CH: RXCE Receive Data Link 3 Control Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
R/W R/W R/W R/W R/W R/W R/W R/W
DL3_EVEN DL3_ODD Unused DL3_TS[4] DL3_TS[3] DL3_TS[2] DL3_TS[1] DL3_TS[0]
0 0 X 0 0 0 0 0
This register, along with the RXCE Data Link 3 Bit Select register, controls the extraction of the data link terminated by RDLC #3. Refer to the "Using the Internal HDLC Receivers" description in the Operation section for details on terminating HDLC frames. DL3_EVEN: The data link 3 even select (DL3_EVEN) bit controls whether or not the third data link is extracted from the even frames of the receive data stream. If DL3_EVEN is a logic 0, the data link is not extracted from the even frames. If DL3_EVEN is a logic 1, the data link is extracted from the even frames. In E1 mode, the frames in an E1 CRC-4 multiframe are considered to be numbered from 0 to 15; in T1 mode, the frames in a superframe are considered to be numbered from 1 to 12 (or 1 to 24 in an extended superframe). DL3_ODD: The data link 3 odd select (DL3_ODD) bit controls whether or not the third data link is extracted from the odd frames of the receive data stream. If DL3_ODD is a logic 0, the data link is not extracted from the odd frames. If DL3_ODD is a logic 1, the data link is extracted from the odd frames. DL3_TS[4:0]: The data link 3 time slot (DL3_TS[4:0]) bits gives a binary representation of the time slot/channel from which the data link is to be extracted. Note that T1 channels 1 to 24 are mapped to values 0 to 23. The DL3_TS[4:0] bits have no effect when DL3_EVEN and DL3_ODD are both a logic 0.
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Register 02DH: RXCE Receive Data Link 3 Bit Select Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
R/W R/W R/W R/W R/W R/W R/W R/W
DL3_BIT[7] DL3_BIT[6] DL3_BIT[5] DL3_BIT[4] DL3_BIT[3] DL3_BIT[2] DL3_BIT[1] DL3_BIT[0]
0 0 0 0 0 0 0 0
DL3_BIT[7:0]: The data link 3 bit select (DL3_BIT[7:0]) bits controls which bits of the time slot/channel are to be extracted and passed to RDLC #3. If DL3_BIT[x] is a logic 1, that bit is extracted as part of the data link. To extract the data link from the entire time slot, all eight DL3_BIT[x] bits must be set to a logic 1. DL3_BIT[7] corresponds to the most significant bit (bit 1, the first bit received) of the time slot and DL3_BIT[0] corresponds to the least significant bit (bit 8, the last bit received) of the time slot. The DL3_BIT[7:0] bits have no effect when the DL3_EVEN and DL3_ODD bits of the RXCE Data Link 3 Control register are both logic 0.
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Register 030H: BRIF Configuration Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 NXDS0[1:0]:
R/W R/W R/W R/W R/W R/W R/W R/W
NXDS0[1] NXDS0[0] CMODE DE FE CMS RATE[1] RATE[0]
0 0 1 1 1 0 0 0
The NXDS0[1:0] bits determine the mode of operation when BRCLK clock master mode is selected, as shown in the following table. Note that these bits are ignored when clock slave mode is selected.
Table 21 NXDS0[1] - Receive Backplane NXDS0 Mode Selection NXDS0[0] Operation
0 0 1 1
0 1 0 1
Full Frame 56 kbit/s NxDS0 64 kbit/s NxDS0 64 kbit/s NxDS0 with F-bit (only valid for E1 mode)
When in Full Frame mode, the entire frame (193 bits for T1 or 256 bits for E1) is presented and the BRCLK pulse train contains no gaps. When in any of the NxDS0 modes, only those time slots with their DTRKC bit cleared (logic 0) are clocked out the backplane. BRCLK does not pulse during those time slots with their DTRKC bit set (logic 1). The DTRKC bits are located in the RPSC Indirect Registers. When in T1 mode, the clock is always gapped during the framing bit position. When the 56 kbit/s NxDS0 mode is selected, only the first 7 bits of the selected time slots are presented to the backplane and the 8th bit is gapped out. When
PROPRIETARY AND CONFIDENTIAL
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the 64 kbit/s NxDS0 mode is selected, all 8 bits of the selected time slots are presented to the backplane. The 64 kbit/s NxDS0 with F-bit mode is intended to support ITU recommendation G.802 where 1.544 Mbit/s data is carried within a 2.048 Mbit/s data stream. This mode is only valid when the E1/T1B register bit is a logic 1 (E1 mode is selected). The operation is the same as the 64 NxDS0 mode, except that the framing bit is presented during the first bit of time slot 26. To properly extract a G.802 formatted T1, the DTRKC bits must be set to logic 0 for time slots 1 through 15 and 17 through 26, and the DTRKC bits must be set to logic 1 for time slots 27 through 31. CMODE: The clock mode (CMODE) bit determines whether the BRCLK pin is an input or output. When CMODE is a logic 0, clock master mode is selected and the BRCLK output is derived from the integral clock synthesizer. Depending on the mode of operation, BRCLK may have a burst frequency of up to 2.048 MHz and may be gapped to support sub-rate applications. In T1 mode, CMODE can only be logic 0 if the backplane rate is 1.544 Mbit/s (RATE[1:0]=00) and CMS=0. In E1 mode, CMODE can only be logic 0 if the backplane rate is 2.048 Mbit/s (RATE[1:0]=01) and CMS=0. When CMODE is a logic 1, clock slave mode is selected and BRCLK is an input. DE: The data edge (DE) bit determines the edge of BRCLK on which BRPCM and BRSIG are generated. If DE is a logic 0, BRPCM and BRSIG are updated on the falling edge of BRCLK. If DE is a logic 1, BRPCM and BRSIG are updated on the rising edge of BRCLK. FE: The framing edge (FE) bit determines the edge of BRCLK on which the frame pulse (BRFP) pulse is sampled or updated. If FE is a logic 0, BRFP is sampled or updated on the falling edge of BRCLK. If FE is a logic 1, BRFP is sampled on the rising edge of BRCLK. In the case where FE is not equal to DE, BRFP is sampled or updated one clock edge before BRPCM and BRSIG. CMS: The clock mode select (CMS) bit determines the BRCLK frequency multiple. If CMS is a logic 0, BRCLK is at the backplane rate. If CMS is a logic 1, BRCLK is at twice the backplane rate.
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RATE[1:0]: The rate select (RATE[1:0]) bits determine the backplane rate according to the following table:
Table 22 RATE[1] - Receive Backplane Rate RATE[0] Backplane Rate
0 0 1 1
0 1 0 1
1.544 Mbit/s 2.048 Mbit/s 4.096 Mbit/s 8.192 Mbit/s
The 4.096 Mbit/s and 8.192 Mbit/s rates are only supported in clock slave mode (CMODE logic 1) with RXELSTBYP logic 0. The RATE[1:0] bits can only be set once after reset.
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Register 031H: BRIF Frame Pulse Configuration Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 MAP:
R/W R/W R/W R/W R/W R/W R/W R/W
MAP FPINV FPMODE ALTFDL ROHM BRXSMFP BRXCMFP ALTBRFP
0 0 1 0 0 0 0 0
The MAP bit determines the mapping of a 2.048 MHz backplane onto a 1.544 MHz line. This bit is ignored when in E1 mode (E1/T1B register bit is logic 1), when the backplane rate is 1.544 Mbit/s (RATE[1:0] = 'b00), or when in clock master mode (CMODE = 'b0). When MAP is a logic 0, every fourth time slot is unused, starting with time slot 0. The framing bit is presented during bit 0 of time slot 0, so that only bits 1 to 7 of time slot 0 are unused. When MAP is a logic 1, the first 24 time slots (0 to 23) are used. The framing bit is sampled during bit 7 of time slot 31 and the rest of the frame (time slots 24 to 30 and bits 0 to 6 of time slot 31) does not contain valid data. FPINV: The frame pulse inversion (FPINV) bit determines whether BRFP is inverted prior to sampling or presentation. If FPINV is a logic 0, BRFP is active high. If FPINV is a logic 1, BRFP is active low. FPMODE: The frame pulse mode (FPMODE) bit determines whether BRFP is an input or an output. When FPMODE is a logic 0, frame pulse master mode is selected, BRFP is an output and the ROHM, BRXSMFP, BRXCMFP and ALTBRFP bits determine what BRFP connotes.
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When FPMODE is a logic 1, frame pulse slave mode is selected and BRFP is an input. When configured as an input, BRFP only has effect when the elastic store is in use (RXELSTBYP is logic 0); otherwise, it is ignored. ALTFDL: In T1 mode, the ALTFDL bit enables the framing bit position on the backplane PCM output to contain a copy of the FDL bit. When ALTFDL is set to logic 1, each M-bit value in the ESF-formatted stream is duplicated and replaces the subsequent CRC bit or F-bit in the output signal stream on BRPCM. When ALTFDL is set to logic 0, the output BRPCM stream contains the received M, CRC, or F bits in the framing bit position. Note that this function is only valid for ESF-formatted streams, ALTFDL should be set to logic 0 when other framing formats are being received. This bit is ignored in E1 mode. ALTBRFP: The ALTBRFP bit suppresses every second output pulse on the backplane output BRFP. When ALTBRFP is set to logic 1 and BRXCMFP and BRXSMP bits are both logic 0, the output signal on BRFP pulses every 386 bits or 512 bits, indicating the first bit of every second frame. Under this condition, BRFP indicates the Signaling Alignment bits (S1-S6) for T1 SF, the data link bits for T1 ESF and the NFAS frames for E1. If the BRXCMFP or BRXSMFP bit is logic 1 when ALTBRFP is logic 1, the output signal on BRFP pulses every 24, 32 or 48 frames. In T1 mode, this latter setting (i.e. both ALTBRFP and BRXSMFP set to logic 1) is useful for converting SF formatted data to ESF formatted data between two COMET devices. When ALTBRFP is set to logic 0, the output signal on BRFP pulses in accordance to the ROHM, BRXCMFP and BRXSMP bit settings. ALTBRFP has no effect if the FPMODE bit or the ROHM bit is a logic 1.
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ROHM, BRXSMFP, BRXCMFP: The ROHM, BRXSMFP and BRXCMFP bits select the output signal seen on the backplane output BRFP. These register bits only have effect if the FPMODE bit is a logic 0. In T1 mode, only BRXSMFP has effect, the other two bits are ignored. When set to logic 1, the BRFP output pulses high during the first framing bit of the 12 frame SF or the 24 frame ESF (depending on the framing format selected in the T1-FRMR ). When BRXSMFP is set to logic 0, the BRFP output pulses high during each framing bit (i.e. every 193 bits). The following table summarizes the configurations for E1 mode:
Table 23 ROHM - E1 Receive Backplane Frame Pulse Configurations BRXSMFP BRXCMFP Result
0
0
0
Backplane receive frame pulse output: BRFP pulses high for 1 BRCLK cycle during bit 1 of each 256-bit frame, indicating the frame alignment of the BRPCM data stream.
0
0
1
Backplane receive CRC multiframe output: BRFP pulses high for 1 BRCLK cycle during bit 1 of frame 1 of every 16 frame CRC multiframe, indicating the CRC multiframe alignment of the BRPCM data stream. (Even when CRC multiframing is disabled, the BRFP output continues to indicate the position of bit 1 of the FAS frame every 16th frame).
0
1
0
Backplane receive signaling multiframe output: BRFP pulses high for 1 BRCLK cycle during bit 1 of frame 1 of the 16 frame signaling multiframe, indicating the signaling multiframe alignment of the BRPCM data stream. (Even when signaling multiframing is disabled, the BRFP output continues to indicate the position of bit 1 of every 16th frame.)
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ROHM
BRXSMFP
BRXCMFP
Result
0
1
1
Backplane receive composite multiframe output: BRFP goes high on the active BRCLK edge marking the beginning of bit 1 of frame 1 of every 16 frame signaling multiframe, indicating the signaling multiframe alignment of the BRPCM data stream, and returns low on the active BRCLK edge marking the end of bit 1 of frame 1 of every 16 frame CRC multiframe, indicating the CRC multiframe alignment of the BRPCM data stream. This mode allows both multiframe alignments to be decoded externally from the single BRFP signal. Note that if the signaling and CRC multiframe alignments are coincident, BRFP will pulse high for 1 BRCLK cycle every 16 frames.
1
X
X
Backplane receive overhead output: BRFP is high for timeslot 0 and timeslot 16 of each 256-bit frame, indicating the overhead of the BRPCM data stream.
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Register 032H: BRIF Parity/F-bit Configuration Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
R/W R/W R/W R/W R/W R/W R/W
RPTYP RPTYE FIXF FIXPOL PTY_EXTD Unused TRI[1] TRI[0]
0 0 0 0 0 X 0 0
This register provides control of data integrity checking on the receive backplane interface. A single parity bit in the F-bit position represents parity over the previous frame (including the undefined bit positions). If a 2.048 Mbit/s backplane rate is selected, the parity calculation is performed over all bit positions, including the undefined positions. Signaling parity is similarly calculated over all bit positions. Parity checking and generation is not supported when the NxDS0 mode is active. Parity checking and generation is not supported when mapping a 1.544 Mbit/s signal onto a higher rate backplane in the format where the first 24 time slots are used, i.e., the RATE[1:0] bits in the BRIF Configuration register are not set to "00" and the MAP bit in the BRIF Frame Pulse Configuration register is logic 1. RPTYP: The receive parity type (RPTYP) bit sets even or odd parity in the receive streams. If RPTYP is a logic 0, the expected parity value in the F-bit position of BRPCM and BRSIG is even, thus it is a one if the number of ones in the previous frame is odd. If RPTYP is a logic 1, the expected parity value in the F-bit position if BRPCM and BRSIG is odd, thus it is a one if the number of ones in the previous frame is even. RPTYP only has effect if RPRTYE is a logic one. RPRTYE: The RPRTYE bit enables receive parity insertion. When set a logic one, parity is inserted into the F-bit position of the BRPCM and BRSIG streams. When set to logic zero, the F-bit passes through transparently.
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FIXF: If the RPRTYE bit is a logic 0, a logic 1 in the FIXF bit forces the first bit of the BRPCM frame (F-bit for T1) to the polarity specified by the FIXPOL bit. If RPRTYE is a logic 1, FIXF has no effect. If RPRTYE and FIXF are both logic 0, the first bit of the frame passes from the line transparently. FIXPOL: This bit determines the logic level of the first bit of the BRPCM frame when the FIXF bit is a logic 1 and the RPRTYE bit is a logic 0. If FIXPOL is a logic 1, BRPCM will be high in the first bit of the frame. If FIXPOL is a logic 0, BRPCM will be low in the first bit of the frame. PTY_EXTD: The parity extend (PRY_EXTD) bit determines the scope of the parity calculation. When PTY_EXTD is logic 1, the parity is calculated over the previous frame plus the previous parity bit. When it is logic 0, the parity is calculated only over the previous frame. TRI[1:0]: The tri-state control bits determine when the BRPCM and BRSIG outputs are high impedance.
Table 24 TRI[1] - Receive Backplane Tri-state Control TRI[0] Effect
0
0
BRPCM and BRSIG are held high impedance. This default ensures the outputs are high impedance during reset and configuration Totem-pole operation. BRPCM and BRSIG drive during the bit periods that contain valid data, i.e. every second or fourth byte for multiplexed operation. Open-drain operation. BRPCM and BRSIG are driven low to indicate a zero. BRPCM and BRSIG are high impedance otherwise. Reserved
0
1
1
0
1
1
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Register 033H: BRIF Time Slot Offset Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TSOFF[6:0]: R/W R/W R/W R/W R/W R/W R/W
Unused TSOFF[6] TSOFF[5] TSOFF[4] TSOFF[3] TSOFF[2] TSOFF[1] TSOFF[0]
X 0 0 0 0 0 0 0
The time slot offset (TSOFF[6:0]) bits give a binary representation of the fixed byte offset between the backplane receive frame pulse (BRFP) and the start of the next frame on the backplane receive data signal (BRPCM). The seven bits can give an offset from 0 - 127 bytes. With a data rate of 2.048 Mbit/s, every byte on BRPCM is driven. With a data rate of 4.096 Mbit/s, every second byte on BRPCM is driven. With a data rate of 8.192 Mbit/s, every fourth byte on BRPCM is driven.
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Register 034H: BRIF Bit Offset Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 BOFF_EN: R/W R/W R/W R/W
Unused Unused Unused Unused BOFF_EN BOFF[2] BOFF[1] BOFF[0]
X X X X 0 0 0 0
The bit offset enable (BOFF_EN) bit is used to enable the bit offset bits. If BOFF_EN is a logic 0, the bit offset is disabled and there is no bit offset between the frame pulse and the first bit of the first time slot. In this case, the BOFF[2:0] bits are ignored. If BOFF_EN is a logic 1, the bit offset is enabled and the BOFF[2:0] bits operate as described below. BOFF[2:0]: The bit offset (BOFF[2:0]) bits gives a binary representation of the fixed offset between the backplane receive frame pulse (BRFP) and the start of the first bit of the first time slot. This binary representation is then used to determine the BRCLK edge, defined as CET (clock edge transmit) on which the first bit of the first time slot is sampled. For example, if CET is 4, the data on BRPCM and BRSIG is sampled on the fourth clock edge after BRFP is sampled (see Figure 11). The following tables show the relationship between BOFF[2:0], FE, DE and CER.
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Table 25 FE DE
- Receive Backplane Bit Offset for CMS = 0 BOFF[2:0]
000 0 0 1 1
Table 26 FE DE
001 6 5 5 6
010 8 7 7 8
011 10 9 9 10
100 12 11 11 12
101 14 13 13 14
110 16 15 15 16
111 18 17 17 18 CET
0 1 0 1
4 3 3 4
- Receive Backplane Bit Offset for CMS = 1 BOFF[2:0]
000 0 0 1 1 0 1 0 1 4 3 3 4
001 8 7 7 8
010 12 11 11 12
011 16 15 15 16
100 20 19 19 20
101 24 23 23 24
110 28 27 27 28
111 32 31 31 32 CET
The above tables are consistent with the convention established by the Concentration Highway Interface (CHI) specification. Note that in the case where FE is logic 0, DE is logic 1 and BRFP is configured for a superframe/multiframe mode, the maximum offset is one frame less two bits, rather than one frame less one bit as in all other configurations. In this configuration, the maximum offset is 191 bits at 1.544 Mbit/s, 254 bits at 2.048 Mbit/s, 510 bits at 4.096 Mbit/s and 1022 bits at 8.192 Mbit/s.
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Register 038H: TXCI Transmit Data Link 1 Control Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
R/W R/W R/W R/W R/W R/W R/W R/W
DL1_EVEN DL1_ODD T1_DL_EN DL1_TS[4] DL1_TS[3] DL1_TS[2] DL1_TS[1] DL1_TS[0]
0 0 1 0 0 0 0 0
This register, along with the TXCI Data Link 1 Bit Select register, controls the insertion of the data link generated by TDPR #1. Refer to the "Using the Internal HDLC Transmitters" description in the Operation section for details on terminating HDLC frames. DL1_EVEN: The data link 1 even select (DL1_EVEN) bit controls whether or not the first data link is inserted into the even frames of the receive data stream. If DL1_EVEN is a logic 0, the data link is not inserted into the even frames. If DL1_EVEN is a logic 1, the data link is inserted into the even frames. In E1 mode, the frames in an E1 CRC-4 multiframe are considered to be numbered from 0 to 15; in T1 mode, the frames in a superframe are considered to be numbered from 1 to 12 (or 1 to 24 in an extended superframe). DL1_ODD: The data link 1 odd select (DL1_ODD) bit controls whether or not the first data link is inserted into the odd frames of the receive data stream. If DL1_ODD is a logic 0, the data link is not inserted into the odd frames. If DL1_ODD is a logic 1, the data link is inserted into the odd frames. T1_DL_EN: The T1 data link enable bit allows the generation of the ESF or T1DM data links when in T1 mode. If T1_DL_EN is a logic 1, the ESF, FMS1 and FMS0 bits of the T1 FRMR Configuration register determine the bit locations into which the data link is inserted. When the T1_DL_EN bit is a logic 1, the DL1_EVEN and DL1_ODD bits must both be set to logic 0. This bit must be set to logic 0 when in E1 mode.
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DL1_TS[4:0]: The data link 1 time slot (DL1_TS[4:0]) bits gives a binary representation of the time slot/channel into which the data link is to be inserted. Note that T1 channels 1 to 24 are mapped to values 0 to 23. The DL1_TS[4:0] bits have no effect when DL1_EVEN and DL1_ODD are both a logic 0.
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Register 039H: TXCI Transmit Data Link 1 Bit Select Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
R/W R/W R/W R/W R/W R/W R/W R/W
DL1_BIT[7] DL1_BIT[6] DL1_BIT[5] DL1_BIT[4] DL1_BIT[3] DL1_BIT[2] DL1_BIT[1] DL1_BIT[0]
0 0 0 0 0 0 0 0
DL1_BIT[7:0]: The data link 1 bit select (DL1_BIT[7:0]) bits controls into which bits of the time slot/channel data from TDPR #1 are to be inserted. If DL1_BIT[x] is a logic 1, the data link is inserted into that bit. To insert the data link into the entire time slot, all eight DL1_BIT[x] bits must be set to a logic 1. DL1_BIT[7] corresponds to the most significant bit (bit 1, the first bit transmitted) of the time slot and DL1_BIT[0] corresponds to the least significant bit (bit 8, the last bit transmitted) of the time slot. The DL1_BIT[7:0] bits have no effect when the DL1_EVEN and DL1_ODD bits of the TXCI Data Link 1 Control register are both logic 0.
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Register 03AH: TXCI Transmit Data Link 2 Control Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
R/W R/W R/W R/W R/W R/W R/W
DL2_EVEN DL2_ODD Unused DL2_TS[4] DL2_TS[3] DL2_TS[2] DL2_TS[1] DL2_TS[0]
0 0 X 0 0 0 0 0
This register, along with the TXCI Data Link 2 Bit Select register, controls the insertion of the data link generated by TDPR #2. Refer to the "Using the Internal HDLC Transmitters" description in the Operation section for details on terminating HDLC frames. DL2_EVEN: The data link 2 even select (DL2_EVEN) bit controls whether or not the second data link is inserted into the even frames of the receive data stream. If DL2_EVEN is a logic 0, the data link is not inserted into the even frames. If DL2_EVEN is a logic 1, the data link is inserted into the even frames. In E1 mode, the frames in an E1 CRC-4 multiframe are considered to be numbered from 0 to 15; in T1 mode, the frames in a superframe are considered to be numbered from 1 to 12 (or 1 to 24 in an extended superframe). DL2_ODD: The data link 2 odd select (DL2_ODD) bit controls whether or not the second data link is inserted into the odd frames of the receive data stream. If DL2_ODD is a logic 0, the data link is not inserted into the odd frames. If DL2_ODD is a logic 1, the data link is inserted into the odd frames. DL2_TS[4:0]: The data link 2 time slot (DL2_TS[4:0]) bits gives a binary representation of the time slot/channel into which the data link is to be inserted. Note that T1 channels 1 to 24 are mapped to values 0 to 23. The DL2_TS[4:0] bits have no effect when DL2_EVEN and DL2_ODD are both a logic 0.
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Register 03BH: TXCI Transmit Data Link 2 Bit Select Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
R/W R/W R/W R/W R/W R/W R/W R/W
DL2_BIT[7] DL2_BIT[6] DL2_BIT[5] DL2_BIT[4] DL2_BIT[3] DL2_BIT[2] DL2_BIT[1] DL2_BIT[0]
0 0 0 0 0 0 0 0
DL2_BIT[7:0]: The data link 2 bit select (DL2_BIT[7:0]) bits controls into which bits of the time slot/channel data from TDPR #2 are to be inserted. If DL2_BIT[x] is a logic 1, the data link is inserted into that bit. To insert the data link into the entire time slot, all eight DL2_BIT[x] bits must be set to a logic 1. DL2_BIT[7] corresponds to the most significant bit (bit 1, the first bit transmitted) of the time slot and DL2_BIT[0] corresponds to the least significant bit (bit 8, the last bit transmitted) of the time slot. The DL2_BIT[7:0] bits have no effect when the DL2_EVEN and DL2_ODD bits of the TXCI Data Link 2 Control register are both logic 0.
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Register 03CH: TXCI Transmit Data Link 3 Control Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
R/W R/W R/W R/W R/W R/W R/W
DL3_EVEN DL3_ODD Unused DL3_TS[4] DL3_TS[3] DL3_TS[2] DL3_TS[1] DL3_TS[0]
0 0 X 0 0 0 0 0
This register, along with the TXCI Data Link 3 Bit Select register, controls the insertion of the data link generated by TDPR #3. Refer to the "Using the Internal HDLC Transmitters" description in the Operation section for details on terminating HDLC frames. DL3_EVEN: The data link 3 even select (DL3_EVEN) bit controls whether or not the third data link is inserted into the even frames of the receive data stream. If DL3_EVEN is a logic 0, the data link is not inserted into the even frames. If DL3_EVEN is a logic 1, the data link is inserted into the even frames. In E1 mode, the frames in an E1 CRC-4 multiframe are considered to be numbered from 0 to 15; in T1 mode, the frames in a superframe are considered to be numbered from 1 to 12 (or 1 to 24 in an extended superframe). DL3_ODD: The data link 3 odd select (DL3_ODD) bit controls whether or not the third data link is inserted into the odd frames of the receive data stream. If DL3_ODD is a logic 0, the data link is not inserted into the odd frames. If DL3_ODD is a logic 1, the data link is inserted into the odd frames. DL3_TS[4:0]: The data link 3 time slot (DL3_TS[4:0]) bits gives a binary representation of the time slot/channel into which the data link is to be inserted. Note that T1 channels 1 to 24 are mapped to values 0 to 23. The DL3_TS[4:0] bits have no effect when DL3_EVEN and DL3_ODD are both a logic 0.
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Register 03DH: TXCI Transmit Data Link 3 Bit Select Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
R/W R/W R/W R/W R/W R/W R/W R/W
DL3_BIT[7] DL3_BIT[6] DL3_BIT[5] DL3_BIT[4] DL3_BIT[3] DL3_BIT[2] DL3_BIT[1] DL3_BIT[0]
0 0 0 0 0 0 0 0
DL3_BIT[7:0]: The data link 3 bit select (DL3_BIT[7:0]) bits controls into which bits of the time slot/channel data from TDPR #3 are to be inserted. If DL3_BIT[x] is a logic 1, the data link is inserted into that bit. To insert the data link into the entire time slot, all eight DL3_BIT[x] bits must be set to a logic 1. DL3_BIT[7] corresponds to the most significant bit (bit 1, the first bit transmitted) of the time slot and DL3_BIT[0] corresponds to the least significant bit (bit 8, the last bit transmitted) of the time slot. The DL3_BIT[7:0] bits have no effect when the DL3_EVEN and DL3_ODD bits of the TXCI Data Link 3 Control register are both logic 0.
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Register 040H: BTIF Configuration Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 NXDS0[1:0]:
R/W R/W R/W R/W R/W R/W R/W R/W
NXDS0[1] NXDS0[0] CMODE DE FE CMS RATE[1] RATE[0]
0 0 1 1 1 0 0 0
The NXDS0[1:0] bits determine the mode of operation when BTCLK clock master mode is selected (CMODE logic 0), as shown in the following table. Note that these bits are ignored when clock slave mode is selected (CMODE logic 1).
Table 27 NXDS0[1] - Transmit Backplane NXDS0 Mode Selection NXDS0[0] Operation
0 0 1 1
0 1 0 1
Full Frame 56 kbit/s NxDS0 64 kbit/s NxDS0 64 kbit/s NxDS0 with F-bit (only valid for E1 mode)
When in Full Frame mode, the entire frame (193 bits for T1 or 256 bits for E1) is sampled from the backplane. When in any of the NxDS0 modes, only those time slots with their IDLE_DS0 bit cleared (logic 0) are sampled from the backplane. The other time slots, with their IDLE_DS0 bit set (logic 1), do not contain valid data and will be overwritten with the per-DS0 idle code. The IDLE_DS0 bits are located in the TPSC Indirect registers. When in T1 mode, the clock is always gapped during the framing bit position.
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When the 56 kbit/s NxDS0 mode is selected, only the first 7 bits of the selected time slots are sampled from the backplane and the 8th bit is gapped out. When the 64 kbit/s NxDS0 mode is selected, all 8 bits of the selected time slots are sampled from the backplane. The 64 kbit/s NxDS0 with F-bit mode is intended to support ITU recommendation G.802. This mode is only valid when the E1/T1B register bit is a logic 1 (E1 mode is selected). The operation is the same as the 64 kbit/s NxDS0 mode, except that the framing bit is sampled. The F-bit is always sampled during the first bit of time slot 26. The remaining seven bits of time slot 26 are not sampled. To properly insert a G.802 formatted T1, the IDLE_DS0 bits must be set to logic 0 for time slots 1 through 15 and 17 through 26, and the IDLE_DS0 bits must be set to logic 1 for time slots 27 through 31. CMODE: The clock mode (CMODE) bit determines whether the BTCLK pin is an input or output. When CMODE is a logic 0, clock master mode is selected and the BTCLK output is derived from the integral clock synthesizer. Depending on the mode of operation, BTCLK may have a burst frequency of up to 2.048 MHz and may be gapped to support sub-rate applications. In T1 mode, CMODE can only be logic 0 if the backplane rate is 1.544 Mbit/s (RATE[1:0]=00) and CMS=0. In E1 mode, CMODE can only be logic 0 if the backplane rate is 2.048 Mbit/s (RATE[1:0]=01) and CMS=0. When CMODE is a logic 1, clock slave mode is selected and BTCLK is an input. DE: The data edge (DE) bit determines the edge of BTCLK on which BTPCM and BTSIG are sampled. If DE is a logic 0, BTPCM and BTSIG are sampled on the falling edge of BTCLK. If DE is a logic 1, BTPCM and BTSIG are sampled on the rising edge of BTCLK. FE: The framing edge (FE) bit determines the edge of BTCLK on which the frame pulse (BTFP) pulse is sampled or updated. If FE is a logic 0, BTFP is sampled or updated on the falling edge of BTCLK. If FE is a logic 1, BTFP is sampled or updated on the rising edge of BTCLK. In the case where FE is not equal to DE, BTFP is sampled one clock edge or updated three clock edges before BTPCM and BTSIG are sampled. CMS: The clock mode select (CMS) bit determines the BTCLK frequency multiple. If CMS is a logic 0, BTCLK is at the backplane rate. If CMS is a logic 1,
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BTCLK is at twice the backplane rate. CMS must be programmed to logic 0 when CMODE=0. RATE[1:0]: The rate select (RATE[1:0]) bits determine the backplane rate according to the following table:
Table 28 RATE[1] - Transmit Backplane Rate RATE[0] Backplane Rate
0 0 1 1
0 1 0 1
1.544 Mbit/s 2.048 Mbit/s 4.096 Mbit/s 8.192 Mbit/s
The 4.096 Mbit/s and 8.192 Mbit/s rates are only supported in clock slave mode (CMODE logic 1). The RATE[1:0] bits can only be set once after reset.
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Register 041H: BTIF Frame Pulse Configuration Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 MAP:
R/W
MAP Unused Unused Unused
0 X X X 0 0 0 1
R/W R/W R/W R/W
FPINV ESF_EN FPTYP FPMODE
The MAP bit determines the mapping of a 2.048 MHz backplane onto a 1.544 MHz line. This bit is ignored when in E1 mode (E1/T1B register bit is logic 1), when the backplane rate is 1.544 Mbit/s (RATE[1:0] = 'b00), or when in clock master mode (CMODE = 'b0). When MAP is a logic 0, every fourth time slot is unused, starting with time slot 0. The framing bit is sampled during bit 0 of time slot 0, so that only bits 1 to 7 of time slot 0 are ignored. When MAP is a logic 1, the first 24 time slots (0 to 23) are sampled. The framing bit is sampled during bit 7 of time slot 31 and the rest of the frame (time slots 24 to 30 and bits 0 to 6 of time slot 31) are ignored. FPINV: The frame pulse inversion (FPINV) bit determines whether BTFP is inverted prior to sampling. If FPINV is a logic 0, BTFP is active high. If FPINV is a logic 1, BTFP is active low. Frame pulse inversion cannot be used when BTFP is configured as an output (FPMODE is a logic 0). ESF_EN: The extended superframe enable (ESF_EN) bit determines which superframe alignment is used when in T1 mode and FPTYP is a logic 1. When ESF_EN is a logic 0, superframe alignment is chosen and BTFP pulses (FPMODE logic 0) or is expected (FPMODE logic 1) every 12 frames. When ESF_EN is a logic 1, extended superframe alignment is chosen and pulses (FPMODE logic 0) or is expected (FPMODE logic 1) every 24 frames.
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This bit is ignored when in E1 mode or in T1 mode when FPTYP is a logic 0. FPTYP: The frame pulse type (FPTYP) bit determines the type of frame pulse on BTFP. When FPTYP is a logic 0, basic frame alignment is chosen and frame pulses occur every frame. When FPTYP is a logic 1, multiframe alignment is chosen. In T1 mode, with multiframe alignment pulses (FPMODE logic 0) or is expected (FRMODE logic 1) every 12 or 24 frames as determined by the ESF_EN bit. In E1 mode, with multiframe alignment when FPMODE is a logic 0, as an output BTFP pulses once every 16 frames to indicate both CRC and signaling multiframe alignment. When BTFP is configured as an input, must be brought high to mark bit 1 of frame 1 of every 16 frame signaling multiframe and brought low following bit 1 of frame 1 of every 16 frame CRC multiframe. To properly initialize the transmit HDLC controllers in basic frame alignment mode (FPTYP is logic 0), multiframe alignment (FPTYP is logic 1) must be configured for at least one multiframe (i.e., for at least one multiframe period in frame pulse master mode or for at least one input frame pulse in frame pulse slave mode). After this initialization, the FPTYP can be set to any desired value. FPMODE: The frame pulse mode (FPMODE) bit determines whether BTFP is an input or an output. When FPMODE is a logic 0, frame pulse master mode is selected and BTFP is an output. When FPMODE is a logic 1, frame pulse slave mode is selected and BTFP is an input. Frame pulse master mode cannot be used with transmit backplane clock rates greater than 2.048 MHz.
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Register 042H: BTIF Parity Configuration and Status Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
R/W R/W R R R/W
TPTYP TPTYE TDI TSIGI PTY_EXTD Unused Unused Unused
0 0 X X 0 X X X
This register provides control and status reporting of data integrity checking on the transmit backplane interface. A single parity bit in the F-bit position represents parity over the previous frame (including the undefined bit positions). Parity checking and generation is not supported when the NxDS0 mode is active. Parity checking and generation is not supported when mapping a 1.544 Mbit/s signal onto a higher rate backplane in the format where the first 24 time slots are used, i.e., the RATE[1:0] bits in the BTIF Configuration register are not set to "00" and the MAP bit in the BTIF Frame Pulse Configuration register is logic 1. TPTYP: The transmit parity type (TPTYP) bit sets even or odd parity in the transmit streams. If TPTYP is a logic 0, the expected parity value in the F-bit position of BTPCM and BTSIG is even, thus it is a one if the number of ones in the previous frame is odd. If TPTYP is a logic 1, the expected parity value in the F-bit position if BTPCM and BTSIG is odd, thus it is a one if the number of ones in the previous frame is even. TPTYE: The transmit parity enable (TPTYE) bit enables transmit parity interrupts. When TPTYE is a logic 1, parity errors on the inputs BTPCM and BTSIG are indicated by the TDI and TSIGI bits, respectively, and by the assertion low of the INTB output. When TPTYE is a logic 0, parity errors are indicated by the TDI and TSIGI bits but are not indicated on the INTB output. TDI: The transmit data interrupt (TDI) bit indicates if a parity error has been detected on the BTPCM input. This bit is cleared when this register is read.
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TSIGI: The transmit signaling interrupt (TSIGI) bit indicated if a parity error has been detected on the BTSIG input. This bit is cleared when this register is read. PTY_EXTD: The parity extend (PRY_EXTD) bit causes the parity to be calculated over the previous frame plus the previous parity bit, instead of only the previous frame.
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Register 043H: BTIF Time Slot Offset Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TSOFF[6:0]: R/W R/W R/W R/W R/W R/W R/W
Unused TSOFF[6] TSOFF[5] TSOFF[4] TSOFF[3] TSOFF[2] TSOFF[1] TSOFF[0]
X 0 0 0 0 0 0 0
The time slot offset (TSOFF[6:0]) bits give a binary representation of the fixed byte offset between the backplane transmit frame pulse (BTFP) and the start of the next frame on the backplane transmit data signal (BTPCM). The seven bits can give an offset from 0 - 127 bytes. With a data rate of 2.048 Mbit/s, every byte on BTPCM is sampled. With a data rate of 4.096 Mbit/s, every second byte on BTPCM is sampled. With a data rate of 8.192 Mbit/s, every fourth byte on BTPCM is sampled.
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Register 044H: BTIF Bit Offset Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 BOFF_EN: R/W R/W R/W R/W
Unused Unused Unused Unused BOFF_EN BOFF[2] BOFF[1] BOFF[0]
X X X X 0 0 0 0
The bit offset enable (BOFF_EN) bit is used to enable the bit offset bits. If BOFF_EN is a logic 0, the bit offset is disabled and there is no bit offset between the frame pulse and the first bit of the first time slot. In this case, the BOFF[2:0] bits are ignored. If BOFF_EN is a logic 1, the bit offset is enabled and the BOFF[2:0] bits operate as described below. BOFF[2:0]: The bit offset (BOFF[2:0]) bits gives a binary representation of the fixed offset between the backplane transmit frame pulse (BTFP) and the start of the first bit of the first time slot. This binary representation is then used to determine the BTCLK edge, defined as CER (clock edge receive) on which the first bit of the first time slot is sampled. For example, if CER is 4, the data on BTPCM and BTSIG is sampled on the fourth clock edge after BTFP is sampled (see Figure 11). The following tables show the relationship between BOFF[2:0], FE, DE and CER.
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Table 29 FE DE
- Transmit Backplane Bit Offset for CMS = 0 BOFF[2:0]
000 0 0 1 1
Table 30 FE DE
001 6 5 5 6
010 8 7 7 8
011 10 9 9 10
100 12 11 11 12
101 14 13 13 14
110 16 15 15 16
111 18 17 17 18 CER
0 1 0 1
4 3 3 4
- Transmit Backplane Bit Offset for CMS = 1 BOFF[2:0]
000 0 0 1 1 0 1 0 1 6 7 7 6
001 10 11 11 10
010 14 15 15 14
011 18 19 19 18
100 22 23 23 22
101 26 27 27 26
110 30 31 31 30
111 34 35 35 34 CER
The above tables are consistent with the convention established by the Concentration Highway Interface (CHI) specification.
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Register 048H: T1 FRMR Configuration Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
R/W R/W R/W R/W R/W R/W R/W
M2O[1] M2O[0] ESFFA ESF FMS1 FMS0 JPN Unused
0 0 0 0 0 0 0 X
When the E1/T1B bit of the Global Configuration register is a logic 1 or the UNF bit of the Receive Options register is a logic 1, this register is held reset. This register selects the framing format and the frame loss criteria used by the T1-FRMR. M2O[1:0]: The M2O[1:0] bits select the ratio of errored to total framing bits before declaring out of frame in SF, SLC(R)96, and ESF framing formats. A logic 00 selects 2 of 4 framing bits in error; a logic 01 selects 2 of 5 bits in error; a logic 10 selects 2 of 6 bits in error. In T1DM framing format, the ratio of errored to total framing bits before declaring out of frame is always 4 out of 12. A logic 11 in the M2O[1:0] bits is reserved and should not be used. ESFFA: The ESFFA bit selects one of two framing algorithms for ESF frame search in the presence of mimic framing patterns in the incoming data. A logic 0 selects the ESF algorithm where the FRMR does not declare inframe while more than one framing bit candidate is following the framing pattern in the incoming data. A logic 1 selects the ESF algorithm where a CRC-6 calculation is performed on each framing bit candidate, and is compared against the CRC bits associated with the framing bit candidate to determine the most likely framing bit position. ESF: The ESF bit selects either extended superframe format or enables the Frame Mode Select bits to select either standard superframe, T1DM, or SLC(R)96
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framing formats. A logic 1 in the ESF bit position selects ESF; a logic 0 bit enables FMS1 and FMS0 to select SF, T1DM, or SLC(R)96. FMS1,FMS0: The FMS1 and FMS0 bits select standard superframe, T1DM, or SLC(R)96 framing formats. A logic 00 in these bits enable the SF framing format; a logic 01 or 11 in these bit positions enable the T1DM framing format; a logic 10 in these bit positions enable the SLC(R)96 framing format. When ESF is selected (ESF bit set to logic 1), the FMS1 and FMS0 bits select the data rate and the source channel for the facility data link data. A logic 00 in these bits enable the FRMR to receive FDL data at the full 4 kHz rate from every odd frame. When ESF is selected, FMS1 and FMS0 settings other than logic 00 are reserved and should not be used. The valid combinations of the ESF, FMS1, and FMS0 bits are summarized in the table below:
Table 31 ESF - T1 Framing Modes FMS0 Mode
FMS1
0 0 0 0 1 1 1 1 JPN:
0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1
Select SF framing format Select T1DM framing format Select SLC96 framing format Select T1DM framing format Select ESF framing format & 4 kHz FDL Data Rate Reserved Reserved Reserved
The JPN bit enables Japanese variations of the standard framing formats. If the JPN bit is a logic 1 and the ESF format is selected (ESF bit is logic 1), the T1-FRMR complies to TTC JT-G704. If the JPN bit is a logic 1 and a nonth ESF format is selected (ESF bit is logic 0), it is assumed the 12 F-bit of the superframe carries a far end receive failure alarm. The alarm is extracted and the framing is modified to be robust when the alarm is active.
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Register 049H: T1 FRMR Interrupt Enable Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W R/W R/W R/W R/W R/W R/W
Unused Reserved COFAE FERE BEEE SFEE MFPE INFRE
X 0 0 0 0 0 0 0
When the E1/T1B bit of the Global Configuration register is a logic 1 or the UNF bit of the Receive Options register is a logic 1, this register is held reset. This register selects which of the MFP, COFA, FER, BEE, SFE or INFR events generates an interrupt on the microprocessor INTB pin when their state changes or their event condition is detected. Reserved: The Reserved bit is used for production test purposes only. The Reserved bit must be programmed to logic 0 for normal operation. COFAE: The COFAE bit enables the generation of an interrupt when the frame find circuitry determines that frame alignment has been achieved and that the new alignment differs from the previous alignment. When COFAE is set to logic 1, the declaration of a change of frame alignment is allowed to generate an interrupt. When COFAE is set to logic 0, a change in the frame alignment does not generate an interrupt on the INTB pin. FERE: The FERE bit enables the generation of an interrupt when a framing bit error has been detected. When FERE is set to logic 1, the detection of a framing bit error is allowed to generate an interrupt. When FERE is set to logic 0, any error in the framing bits does not generate an interrupt on the INTB pin.
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BEEE: The BEEE bit enables the generation of an interrupt when a bit error event has been detected. A bit error event is defined as framing bit errors for SF formatted data, CRC-6 mismatch errors for ESF formatted data, Ft bit errors for SLC(R)96 formatted data, and either framing bit errors or sync word errors for T1DM formatted data. When BEEE is set to logic 1, the detection of a bit error event is allowed to generate an interrupt. When BEEE is set to logic 0, bit error events are disabled from generating an interrupt on the INTB pin. SFEE: The SFEE bit enables the generation of an interrupt when a severely errored framing event has been detected. A severely errored framing event is defined as 2 or more framing bit errors during the current superframe for SF, ESF, or SLC(R)96 formatted data, and 2 or more framing bit errors or sync word errors during the current superframe for T1DM formatted data. When SFEE is set to logic 1, the detection of a severely errored framing event is allowed to generate an interrupt. When SFEE is set to logic 0, severely errored framing events are disabled from generating an interrupt on the INTB pin. MFPE: The MFPE bit enables the generation of an interrupt when the frame find circuitry detects the presence of framing bit mimics. The occurrence of a mimic is defined as more than one framing bit candidate following the frame alignment pattern. When MFPE is set to logic 1, the assertion or deassertion of the detection of a mimic is allowed to generate an interrupt. When MFPE is set to logic 0, the detection of a mimic framing pattern is disabled from generating an interrupt on the INTB pin. INFRE: The INFRE bit enables the generation of an interrupt when the frame find circuitry determines that frame alignment has been achieved and that the framer is now "inframe". When INFRE is set to logic 1, the assertion or deassertion of the "inframe" state is allowed to generate an interrupt. When INFRE is set to logic 0, a change in the "inframe" state is disabled from generating an interrupt on the INTB pin. Upon reset of the COMET, these bits are set to logic 0, disabling the generation of interrupts on the INTB pin.
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Register 04AH: T1 FRMR Interrupt Status Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
R R R R R R R R
COFAI FERI BEEI SFEI MFPI INFRI MFP INFR
0 0 0 0 0 0 0 0
When the E1/T1B bit of the Global Configuration register is a logic 1 or the UNF bit of the Receive Options register is a logic 1, this register is held reset. This register indicate whether a change of frame alignment, a framing bit error, a bit error event, or a severely errored framing event generated an interrupt. This register also indicates whether a mimic framing pattern was detected or whether there was a change in the "inframe" state of the frame circuitry. COFAI, FERI, BEEI, SFEI: A logic 1 in the status bit positions COFAI, FERI, BEEI and SFEI indicate that the occurrence of the corresponding event generated an interrupt; a logic 0 in the status bit positions COFAI, FERI, BEEI, and SFEI indicate that the corresponding event did not generate an interrupt. MFPI: A logic 1 in the MFPI status bit position indicates that the assertion or deassertion of the mimic detection indication has generated an interrupt; a logic 0 in the MFPI bit position indicates that no change in the state of the mimic detection indication occurred. INFRI: A logic 1 in the INFRI status bit position indicates that a change in the "inframe" state of the frame alignment circuitry generated an interrupt; a logic 0 in the INFRI status bit position indicates that no state change occurred.
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MFP, INFR: The bit position MFP and INFR indicate the current state of the mimic detection and of the frame alignment circuitry. The interrupt and the status bit positions (COFAI, FERI, BEEI, SFEI, MFPI, and INFRI) are cleared to logic 0 when this register is read.
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Register 04CH: IBCD Configuration Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
R/W
Reserved Unused Unused Unused
0 X X X 0 0 0 0
R/W R/W R/W R/W
DSEL1 DSEL0 ASEL1 ASEL0
When the E1/T1B bit of the Global Configuration register is a logic 1, this register is held reset. This register provides the selection of the Activate and De-activate loopback code lengths (from 3 bits to 8 bits) as follows:
Table 32 - Loopback Code Configurations ACTIVATE Code ASEL1 ASEL0 CODE LENGTH
DEACTIVATE Code DSEL1 DSEL0
0 0 1 1
Note:
0 1 0 1
0 0 1 1
0 1 0 1
5 bits 6 (or 3*) bits 7 bits 8 (or 4*) bits
3-bit and 4-bit code sequences can be accommodated by configuring the IBCD for 6 or 8 bits and by programming two repetitions of the code sequence. The Reserved bit is used for production test purposes only. The Reserved bit must be programmed to logic 0 for normal operation.
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Register 04DH: IBCD Interrupt Enable/Status Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
R R R/W R/W R R R R
LBACP LBDCP LBAE LBDE LBAI LBDI LBA LBD
0 0 0 0 0 0 0 0
When the E1/T1B bit of the Global Configuration register is a logic 1, this register is held reset. LBACP, LBDCP: The LBACP and LBDCP bits indicate when the corresponding loopback code is present during a 39.8 ms interval. LBAE: The LBAE bit enables the assertion or deassertion of the inband Loopback Activate (LBA) detect indication to generate an interrupt on the microprocessor INTB pin. When LBAE is set to logic 1, any change in the state of the LBA detect indication generates an interrupt. When LBAE is set to logic 0, no interrupt is generated by changes in the LBA detect state. LBDE: The LBDE bit enables the assertion or deassertion of the inband Loopback Deactivate (LBD) detect indication to generate an interrupt on the microprocessor INTB pin. When LBDE is set to logic 1, any change in the state of the LBD detect indication generates an interrupt. When LBDE is set to logic 0, no interrupt is generated by changes in the LBD detect state. LBAI, LBDI: The LBAI and LBDI bits indicate which of the two expected loopback codes generated the interrupt when their state changed. A logic 1 in these bit positions indicate that a state change in that code has generated an interrupt; a logic 0 in these bit positions indicate that no state change has occurred.
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LBA, LBD: The LBA and LBD bits indicate the current state of the corresponding loopback code detect indication. A logic 1 in these bit positions indicate the presence of that code has been detected; a logic 0 in these bit positions indicate the absence of that code.
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Register 04EH: IBCD Activate Code Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
R/W R/W R/W R/W R/W R/W R/W R/W
ACT7 ACT6 ACT5 ACT4 ACT3 ACT2 ACT1 ACT0
0 0 0 0 0 0 0 0
When the E1/T1B bit of the Global Configuration register is a logic 1, this register is held reset. This 8-bit register selects the Activate code sequence that is to be detected. If the code sequence length is less than 8 bits, the first 8 bits of several repetitions of the code sequence must be used to fill the 8-bit register. For example, if code sequence is a repeating 00001, the first 8 bits of two repetitions (0000100001) is programmed into the register, i.e.00001000. Note that bit ACT7 corresponds to the first code bit received. Upon reset of the COMET, the register contents are set to logic 0.
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Register 04FH: IBCD Deactivate Code Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
R/W R/W R/W R/W R/W R/W R/W R/W
DACT7 DACT6 DACT5 DACT4 DACT3 DACT2 DACT1 DACT0
0 0 0 0 0 0 0 0
When the E1/T1B bit of the Global Configuration register is a logic 1, this register is held reset. This 8-bit register selects the Deactivate code sequence that is to be detected. If the code sequence length is less than 8 bits, the first 8 bits of several repetitions of the code sequence must be used to fill the 8-bit register. For example, if code sequence is a repeating 001, the first 8 bits of three repetitions (001001001) is programmed into the register, i.e.00100100. Note that bit DACT7 corresponds to the first code bit received. Upon reset of the COMET, the register contents are set to logic 0.
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Register 050H: SIGX Configuration Register (COSS = 0) Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reserved:
R/W R/W R/W R/W R/W R/W R/W R/W
Reserved COSS SIGE Reserved Reserved ESF IND PCCE
0 0 0 0 0 0 0 0
These bits must be a logic 0 for correct operation. COSS: The COSS bit allows the channels to be polled to determine in which channel(s) the signaling state has changed. When COSS is a logic 1, the SIGX register space is configured to allow the change of signaling state event bits to be read. When COSS is a logic 0, the SIGX register space is configured to allow indirect access to the configuration and signaling data for each of the 24 T1 or 30 E1 channels. SIGE: The SIGE bit enables a change of signaling state in any one of the 24 channels (T1 mode) or 30 channels for (E1 mode ) to generate an interrupt on the INTB output. When SIGE is set to logic 1, a change of signaling state in any channel generates an interrupt. When SIGE is set to logic 0, the interrupt is disabled. ESF: The framing format in T1 mode is controlled by the ESF bit. A logic 1 in the ESF bit position selects ESF; a logic 0 bit selects SF, SLC(R)96 or T1DM. When in E1 mode, this bit is ignored.
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IND: The IND bit controls the microprocessor access type: either indirect or direct. IND must be logic 1 for proper operation. PCCE: The per-timeslot/per-channel configuration enable bit, PCCE, enables the configuration data in the per-timeslot/per-channel registers to affect the BRSIG and BRPCM data streams. A logic 1 in the PCCE bit position enables the Per-Timeslot/Per-Channel Configuration Register bits in the indirect registers 40H through 5FH; a logic 0 disables the Per-Timeslot/Per-Channel Configuration Register bits in those registers. Please refer to the Per-timeslot/Per-Channel Configuration descriptions for configuration bit details. When the TSB is reset, the PCCE bit is set to logic 0, disabling the Per-Timeslot/Per-Channel Configuration Register bits.
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Register 050H: SIGX Change of Signaling State Register (COSS = 1) Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 COSS[30:25]: R/W R R R R R R
Unused COSS COSS[30] COSS[29] COSS[28] COSS[27] COSS[26] COSS[25]
X 0 X X X X X X
The COSS[30:25] bits will be set to logic 1 if a change of signaling state occurs on the corresponding E1 timeslot. COSS[30:25] are cleared after this register is read. COSS[30:25] are valid only if the E1/T1B register bit is a logic 1. The COSS bit allows the timeslot to be polled to determine in which timeslot(s) the signaling state has changed. When COSS is a logic 1, the SIGX register space is configured to allow the change of signaling state event bits to be read. When COSS is a logic 0, the SIGX register space is configured to allow indirect access to the configuration and signaling data for each of the 24 T1 or 30 E1 channels. COSS[25] through COSS[30] correspond to timeslots 26 through 31.
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Register 051H: SIGX Timeslot Indirect Status (COSS = 0) Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
R
BUSY Unused Unused Unused Unused Unused Unused Unused
0 X X X X X X X
The Timeslot Indirect Status Register is provided at SIGX read/write address 1. BUSY: The BUSY bit is set to logic 1 while the timeslot data is being retrieved or while the configuration data is being written. The bit is set to logic 0 when the read or write cycle has been completed. The BUSY signal holds off a microprocessor read or write access until the SIGX has completed the previous request. This register should be polled until the BUSY bit is logic 0. The bits in this register are valid only when COSS = 0.
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Register 051H: SIGX Change Of Signaling State Change (COSS=1) Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 COSS[24:17]:
R R R R R R R R
COSS[24] COSS[23] COSS[22] COSS[21] COSS[20] COSS[19] COSS[18] COSS[17]
X X X X X X X X
The COSS[24:17] bits will be set to logic 1 if a change of signaling state occurs on the corresponding E1 timeslot OR T1 channel. COSS[24:17] are cleared after this register is read. In E1 mode, COSS[17] through COSS[24] correspond to timeslots 18 through 25. For the purposes of signaling extraction, the T1 channels are indexed 1 through 24.
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Register 052H: SIGX Timeslot Indirect Address/Control (COSS = 0) Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
R/W R/W R/W R/W R/W R/W R/W R/W
RWB A[6] A[5] A[4] A[3] A[2] A[1] A[0]
0 0 0 0 0 0 0 0
If the SIGX is enabled for direct microprocessor access, writing to and reading from the Timeslot Indirect Address Register will not generate any additional accesses. A[6:0]: If the SIGX is enabled for indirect microprocessor access, writing to the Timeslot Indirect Address Register initiates a microprocessor access request to one of the registers in segments 2 and 3. The desired register is addressed using the value written to bits A[6:0]. RWB: The RWB bit indicates which operation is requested. If RWB is set to logic 1, a read is requested. After the request has been issued, the Timeslot Indirect Status register should be monitored to verify completion of the read. The desired register contents can then be found in the Timeslot Indirect Data Register. If RWB is set to logic 0, a write is requested. Data to be written to the microprocessor should first be placed in the Timeslot Indirect Data Register. For both read and write operations, the BUSY bit in the Timeslot Indirect Status Register should be monitored to ensure that the previous access has been completed. Note: If the value written to A[6:0] addresses a segment 1 register, an access is not initiated.
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Register 052H: SIGX Change of Signaling State Register (COSS = 1) Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 COSS[16:9]:
R R R R R R R R
COSS[16] COSS[15] COSS[14] COSS[13] COSS[12] COSS[11] COSS[10] COSS[9]
X X X X X X X X
The COSS[16:9] bits will be set to logic 1 if a change of signaling state occurs on the corresponding E1 timeslot or T1 channel. COSS[16:9] are cleared after this register is read. In E1 mode, COSS[9] through COSS[15] correspond to timeslots 9 through 15 and COSS[16] corresponds to timeslot 17. For the purposes of signaling extraction, the T1 channels are indexed 1 through 24.
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Register 053H: SIGX Timeslot Indirect Data Buffer (COSS = 0) Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
R/W R/W R/W R/W R/W R/W R/W R/W
D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0]
X X X X X X X X
In the case of an indirect write, the Indirect Data Register holds the value that will be written to the desired register when a write is initiated via the Timeslot Indirect Address Register. In the case of an indirect read, the Indirect Data Register will hold the contents of the indirectly addressed register, when the read has been completed. Please refer below to the per-timeslot register descriptions for the expected bit formats.
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Register 053H: SIGX Change of Signaling State (COSS = 1) Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 COSS[8:1]:
R R R R R R R R
COSS[8] COSS[7] COSS[6] COSS[5] COSS[4] COSS[3] COSS[2] COSS[1]
X X X X X X X X
The COSS[8:1] bits will be set to logic 1 if a change of signaling state occurs on the corresponding E1 timeslot or T1 channel. COSS[8:1] are cleared after this register is read. In E1 mode, COSS[1] through COSS[8] correspond to timeslots 1 through 8. For the purposes of signaling extraction, the T1 channels are indexed 1 through 24.
SIGX Indirect Registers
The signaling and per-timeslot functions are allocated within the indirect registers as follows:
Table 33 Addr - SIGX Indirect Register Map Register
10H 11H 12H 13H 14H 15H
Current Signaling Data Register for Ch 1 and 17 Current Signaling Data Register for TS1 and 17/Ch 2 and 18 Current Signaling Data Register for TS2 and 18/Ch 3 and 19 Current Signaling Data Register for TS3 and 19/Ch 4 and 20 Current Signaling Data Register for TS4 and 20/Ch 5 and 21 Current Signaling Data Register for TS5 and 21/Ch 6 and 22
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Addr
Register
16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 20H 21H 22H
* * *
Current Signaling Data Register for TS6 and 22/Ch 7 and 23 Current Signaling Data Register for TS7 and 23/Ch 8 and 24 Current Signaling Data Register for TS8 and 24/Ch 9 Current Signaling Data Register for TS9 and 25/Ch 10 Current Signaling Data Register for TS10 and 26/Ch 11 Current Signaling Data Register for TS11 and 27/Ch 12 Current Signaling Data Register for TS12 and 28/Ch 13 Current Signaling Data Register for TS13 and 29/Ch 14 Current Signaling Data Register for TS14 and 30/Ch 15 Current Signaling Data Register for TS15 and 31/Ch 16 Delayed Signaling Data Register for Ch 1 Delayed Signaling Data Register for TS1/Ch 2 Delayed Signaling Data Register for TS2/Ch 3
* * *
2FH 30H 31H
* * *
Delayed Signaling Data Register for TS15/Ch 16 Delayed Signaling Data Register for Ch 17 Delayed Signaling Data Register for TS17/Ch 18
* * *
37H 38H
* * *
Delayed Signaling Data Register for TS23/Ch 24 Delayed Signaling Data Register for TS24
* * *
3EH 3FH
Delayed Signaling Data Register for TS30 Delayed Signaling Data Register for TS31
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Addr
Register
40H 41H
* * *
TS0/Ch 1 Configuration Data TS1/Ch 2 Configuration Data
* * *
57H 58H
* * *
TS23/Ch 24 Configuration Data TS24 Configuration Data
* * *
5EH 5FH
TS 30 Configuration Data TS 31 Configuration Data
Table 34 - SIGX Indirect Registers 10H - 1FH: Current Timeslot/Channel Signaling Data Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
R R R R R R R R
A TS/Ch `n' B TS/Ch `n' C TS/Ch `n' D TS/Ch `n' A TS/Ch `n+16' B TS/Ch `n+16' C TS/Ch `n+16' D TS/Ch `n+16'
X X X X X X X X
Timeslot (E1 mode) and Channel (T1 mode) signaling data can be read from the Timeslot/Channel Signaling Data registers. In E1 mode, TS0 and TS16 do not contain valid data and are not available for reading. The signaling data is termed "Current" here because it is available in the same signaling multi-frame that the COSS[x] indication is available. Note that the signaling data is stored in nibble format.
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Table 35 - SIGX Indirect Registers 20H - 3FH: Delayed Timeslot/Channel Signaling Data Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R R R R
Unused Unused Unused Unused A TS/Ch `n' B TS/Ch `n' C TS/Ch `n' D TS/Ch `n'
X X X X X X X X
Timeslot (E1 mode) and Channel (T1 mode) signaling data can be read from the Timeslot/Channel Signaling Data registers. Addresses 20H - 37H are valid in T1 mode. Addresses 20H-3FH correspond to TS 0 - TS31. In E1 mode, TS0 and TS16 do not contain valid data. The signaling data is termed "Delayed" here because it is not available until one full signaling multi-frame after the COSS[x] indication is available.
Table 36 Bit - Indirect Registers 40H - 5FH: Per-Timeslot Configuration Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W R/W R/W R/W
Unused Unused Unused Unused RINV[1] RINV[0]/RFIX RPOL RDEBE
X X X X X X X X
RINV[1:0] / RFIX: In T1 mode, the RINV[1] and SIGNINV bit of the RPSC Data Control byte can be used to invert data as shown in Table 37:
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Table 37 RINV[1]
- SIGX Per-Channel T1 Data Conditioning SIGNINV Effect on PCM Channel Data
0 1 0 1
0 0 1 1
PCM Channel data is unchanged All 8 bits of the received PCM channel data are inverted Only the MSB of the received PCM channel data is inverted (SIGN bit inversion) All bits EXCEPT the MSB of the received PCM channel data is inverted (Magnitude inversion)
In E1 mode, the RINV[1:0] bits select bits within the timeslot are inverted. The bit mapping is as shown in Table 38.
Table 38 RINV[1] - SIGX Per-Channel E1 Data Conditioning RINV[0] Effect on PCM Channel Data
0 0 1 1
0 1 0 1
do not invert invert even bits (2,4,6,8) invert odd bits (1,3,5,7) invert all bits
Because of the distinct requirements for E1 and T1, the register bits have different definitions in the two modes. In E1 mode bit 2 is defined as RINV[0]; whereas in T1 it is RFIX. RINV[1] has a different effect for the two modes. In T1 mode, RFIX controls whether the signaling bit (the least significant bit of the DS0 channel on BRPCM during signaling frames) is fixed to the polarity specified by the RPOL bit. A logic 1 in the RFIX position enables bit fixing; a logic 0 in the RFIX position disables bit fixing. Note that the RPSC functions (inversion, digital milliwatt code insertion, trunk conditioning, and PRBS detection or insertion) take place after bit fixing. RPOL: In T1 mode, the RPOL bit selects the logic level the signaling bit is fixed to when bit fixing is enabled. When RPOL is a logic 1, the signaling is fixed to logic 1. When RPOL is a logic 0, the signaling is fixed to logic 0. RDEBE: The RDEBE bit enables debouncing of timeslot/channel signaling bits. A logic 1 in this bit position enables signaling debouncing while a logic 0
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disables it. When debouncing is selected, per-timeslot/per-channel signaling transitions are ignored until two consecutive, equal values are sampled. Debouncing is performed on a per signaling bit basis. Data inversion, data trunk conditioning, and digital milliwatt insertion are performed independently of the received framing format. Digital milliwatt insertion takes precedence over data trunk conditioning which, in turn, takes precedence over the various data inversions. To enable the RINV[1], RINV[0]/RFIX, RPOL, RDEBE bits, the PCCE bit in the SIGX Configuration Register must be set to logic 1.
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Register 054H: T1 XBAS Configuration Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
R/W R/W R/W R/W R/W R/W R/W R/W
MTRK JPN B8ZS ESF FMS1 FMS0 ZCS1 ZCS0
0 0 0 0 0 0 0 0
When the E1/T1B bit of the Global Configuration register is a logic 1, this register is held reset. MTRK: The MTRK bit forces trunk conditioning, idle code substitution and signaling conditioning, on all channels when MTRK is a logic 1. This has the same effect as setting the IDLE_DS0 bit in the PCM Control byte and the SIG0 bit in the SIGNALING Control byte for all channels. JPN: The JPN bit enables Japanese variations of the standard framing formats. If the JPN bit is a logic 1 and the ESF format is selected (ESF bit is logic 1), the XBAS complies to TTC JT-G704. If the JPN bit is a logic 1 and the SF format is selected, the framing bit of frame 12 is forced to logic 1 when a Yellow alarm is declared. Otherwise, bit 2 in all of the channels is forced to logic 0 to indicate Yellow alarm. Framing insertion must be enabled in order to transmit the alternate SF Yellow alarm. B8ZS: The B8ZS bit enables B8ZS line coding when it is a logic 1. When the B8ZS bit is a logic 0, AMI coding is used. ESF, FMS1, FMS0: The ESF bit selects either Extended Superframe format or enables the Frame Mode Select bits (FMS) to select either regular superframe, T1DM or SLC(R)96 framing formats. The mode is encoded as follows:
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Table 39 ESF
- T1 Framing Formats FMS0 MODE
FMS1
0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1
SF framing format T1DM framing format (R bit unaffected) SLC(R)96 T1DM framing format (FDL data replaces R bit) ESF framing format - 4 kbit/s data link Reserved Reserved Reserved
ZCS[1:0]: The ZCS[1:0] bits select the Zero Code Suppression format to be used. These bits are logically ORed with the ZCS[1:0] bits in the TPSC per-channel PCM Control byte. The bits are encoded as follows:
Table 40 ZCS1 - T1 Zero Code Suppression Formats ZCS0 Zero Code Suppression Format
0 0
0 1
None GTE Zero Code Suppression (Bit 8 of an all zero channel byte is replaced by a one, except in signaling frames where bit 7 is forced to a one.) DDS Zero Code Suppression (All zero data byte replaced with "10011000") Bell Zero Code Suppression (Bit 7 of an all zero channel byte is replaced by a one.)
1 1
0 1
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Register 055H: T1 XBAS Alarm Transmit Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W R/W
Unused Unused Unused Unused Unused Unused XYEL XAIS
X X X X X X 0 0
When the E1/T1B bit of the Global Configuration register is a logic 1, this register is held reset. This register controls the transmission of Yellow or AIS alarm. XYEL The XYEL bit enables the XBAS to generate a Yellow alarm in the appropriate framing format. When XYEL is set to logic 1, XBAS is enabled to set bit 2 of each channel to logic 0 for SF and SLC(R)96 formats, the Y-bit to logic 0 for T1DM format, and XBAS is enabled to transmit repetitions of 1111111100000000 (the Yellow Alarm BOC) on the FDL for ESF format. If the JPN bit of the T1-XBAS Configuration register is a logic 1 and the SF format is selected, the framing bit of frame 12 is forced to logic 1 when a Yellow alarm is enabled. When XYEL is set to logic 0, XBAS is disabled from generating the Yellow alarm. XAIS: The XAIS bit enables the XBAS to generate an unframed all-ones AIS alarm. When XAIS is set to logic 1, the XBAS bipolar outputs are forced to pulse alternately, creating an all-ones signal. When XAIS is set to logic 0, the XBAS bipolar outputs operate normally.
PROPRIETARY AND CONFIDENTIAL
193
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Register 056H: T1 XIBC Control Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
R/W R/W
EN UF Unused Unused Unused Unused
0 0 X X X X 0 0
R/W R/W
CL1 CL0
When the E1/T1B bit of the Global Configuration register is a logic 1, this register is held reset. EN: The EN bit controls whether the Inband Code is transmitted or not. A logic 1 in the EN bit position enables transmission of inband codes; a logic 0 in the EN bit position disables inband code transmission. UF: The UF bit controls whether the code is transmitted framed or unframed. A logic 1 in the UF bit position selects unframed inband code transmission; a logic 0 in the UF bit position selects framed inband code transmission. Note: the UF register bit controls the XBAS directly and is not qualified by the EN bit. When UF is set to logic 1, the XBAS is disabled and no framing is inserted regardless of the setting of EN. The UF bit should only be written to logic 1 when the EN bit is set, and should be cleared to logic 0 when the EN bit is cleared. CL1, CL0: The bit positions CL1 and CL0 of this register indicate the length of the inband loopback code sequence, as follows:
Table 41 CL1 - Transmit In-band Code Length CL0 Code Length
0
0
5
PROPRIETARY AND CONFIDENTIAL
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CL1
CL0
Code Length
0 1 1
1 0 1
6 7 8
Codes of 3 or 4 bits in length may be accommodated by treating them as half of a double-sized code (i.e., a 3-bit code would use the 6-bit code length setting).
PROPRIETARY AND CONFIDENTIAL
195
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Register 057H: T1 XIBC Loopback Code Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
R/W R/W R/W R/W R/W R/W R/W R/W
IBC7 IBC6 IBC5 IBC4 IBC3 IBC2 IBC1 IBC0
X X X X X X X X
When the E1/T1B bit of the Global Configuration register is a logic 1, this register is held reset. This register contains the inband loopback code pattern to be transmitted. The code is transmitted most significant bit ( IBC7) first, followed by IBC6 and so on. The code, regardless of the length, must be aligned with the MSB always in the IBC7 position (e.g., a 5-bit code would occupy the IBC7 through IBC2 bit positions). To transmit a 3-bit or a 4-bit code pattern, the pattern must be paired to form a double-sized code (i.e., the 3-bit code '011' would be written as the 6bit code '011011'). When the COMET is reset, the contents of this register are not affected.
PROPRIETARY AND CONFIDENTIAL
196
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COMBINED E1/T1 TRANSCEIVER
Register 058H: PMON Interrupt Enable/Status Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W R R
Unused Unused Unused Unused Unused INTE XFER OVR
X X X X X 0 0 0
This register contains status information indicating when counter data has been transferred into the holding registers and indicating whether the holding registers have been overrun. INTE: The INTE bit controls the generation of a microprocessor interrupt when the transfer clock has caused the counter values to be stored in the holding registers. A logic 1 bit in the INTE position enables the generation of an interrupt via the INTB output; a logic 0 bit in the INTE position disables the generation of an interrupt. XFER: The XFER bit indicates that a transfer of counter data has occurred. A logic 1 in this bit position indicates that a latch request, initiated by writing to one of the counter register locations or the Global PMON Update register, was received and a transfer of the counter values has occurred. A logic 0 indicates that no transfer has occurred. The XFER bit is cleared (acknowledged) by reading this register. OVR: The OVR bit is the overrun status of the holding registers. A logic 1 in this bit position indicates that a previous transfer (indicated by XFER being logic 1) has not been acknowledged before the next transfer clock has been issued and that the contents of the holding registers have been overwritten. A logic 0 indicates that no overrun has occurred. The OVR bit is cleared by reading this register.
PROPRIETARY AND CONFIDENTIAL
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Registers 059-05FH: Latching Performance Data
The Performance Data registers for a single framer are updated as a group by writing to any of the PMON count registers (addresses 059H-05FH). A write to one (and only one) of these locations loads performance data located in the PMON into the internal holding registers. Alternatively, the Performance Data registers are updated by writing to the Revision/Chip ID/Global PMON Update register (address 00DH). The data contained in the holding registers can then be subsequently read by microprocessor accesses into the PMON count register address space. The latching of count data, and subsequent resetting of the counters, is synchronized to the internal event timing so that no events are missed. The PMON is loaded with new performance data within 3.5 recovered clock periods of the latch performance data register write. With nominal line rates, the PMON registers should not be polled until 2.3 sec have elapsed from the "latch performance data" register write. When the COMET is reset, the contents of the PMON count registers are unknown until the first latching of performance data is performed.
PROPRIETARY AND CONFIDENTIAL
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Register 059H: PMON Framing Bit Error Count Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 FER[6:0]: R R R R R R R
Unused FER[6] FER[5] FER[4] FER[3] FER[2] FER[1] FER[0]
X X X X X X X X
The FER[6:0] bits indicate the number of framing bit error events that occurred during the previous accumulation interval. The FER counts are suppressed when the framer has lost frame alignment (OOF in the E1-FRMR Framing Status register is logic 1 or INFR in the T1-FRMR Interrupt Status register is logic 0). In T1 mode, a framing bit error is defined as an Fe-bit error in ESF, a framing bit error in SF, FT-bit error in SLC(R)96, or an F-bit error in T1DM. In E1 mode, the count is either the number of FAS (frame alignment signal) bits (default) or words in error. As an option, a zero in bit 2 of time slot 0 of non-frame alignment signal (NFAS) frames results in an increment of the framing error count. Refer to the Receive Options register.
PROPRIETARY AND CONFIDENTIAL
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Register 05AH: PMON OOF/COFA/Far End Block Error Count LSB Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
R R R R R R R R
OOF/FEBE[7] OOF/FEBE[6] OOF/FEBE[5] OOF/FEBE[4] OOF/FEBE[3] OOF/FEBE[2] OOF/FEBE[1] OOF/FEBE[0]
X X X X X X X X
PROPRIETARY AND CONFIDENTIAL
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Register 05BH: PMON OOF/COFA/Far End Block Error Count MSB Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R R
Unused Unused Unused Unused Unused Unused OOF/FEBE[9] OOF/FEBE[8]
X X X X X X X X
OOF/FEBE[9:0]: In T1 mode, the OOF[9:0] bits indicate the number Out Of Frame or Change Of Frame Alignment events that occurred during the previous accumulation interval, as specified by the CCOFA bit in the Receive Options register. If OOFs are being accumulated, the count is incremented each time a severely errored framing event forces a reframe. IF COFAs are being accumulated, the count is incremented if a new alignment differs from the previous alignment. In E1 mode, the FEBE[9:0] bits indicate the number of far end block error events that occurred during the previous accumulation interval. The FEBE counts are suppressed when the E1 FRMR has lost frame alignment (OOF in the FRMR Framing Status register is set).
PROPRIETARY AND CONFIDENTIAL
201
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Register 05CH: PMON Bit Error/CRC Error Count LSB Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
R R R R R R R R
BEE/CRCE[7] BEE/CRCE[6] BEE/CRCE[5] BEE/CRCE[4] BEE/CRCE[3] BEE/CRCE[2] BEE/CRCE[1] BEE/CRCE[0]
X X X X X X X X
PROPRIETARY AND CONFIDENTIAL
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Register 05DH: PMON Bit Error/CRC Error Count MSB Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R R
Unused Unused Unused Unused Unused Unused BEE/CRCE[9] BEE/CRCE[8]
X X X X X X X X
BEE/CRCE[9:0]: In T1 mode, the BEE[9:0] bits contain the number of bit error events that occurred during the previous accumulation interval. A bit error event is defined as a CRC-6 error in ESF, a framing bit error in SF, an FT-bit error in SLC(R)96, and an F-bit or sync bit error (there can be up to 7 bits in error per frame) in T1DM. In E1 mode, the CRCE[9:0] bits indicate the number of CRC error events that occurred during the previous accumulation interval. CRC error events are suppressed when the E1 FRMR is out of CRC-4 multiframe alignment (OOCMF bit in the FRMR Framing Status register is set).
PROPRIETARY AND CONFIDENTIAL
203
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Register 05EH: PMON LCV Count (LSB) Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
R R R R R R R R
LCV[7] LCV[6] LCV[5] LCV[4] LCV[3] LCV[2] LCV[1] LCV[0]
X X X X X X X X
PROPRIETARY AND CONFIDENTIAL
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Register 05FH: PMON LCV Count (MSB) Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 LCV[12:0]: R R R R R
Unused Unused Unused LCV[12] LCV[11] LCV[10] LCV[9] LCV[8]
X X X X X X X X
The LCV[12:0] bits indicate the number of LCV error events that occurred during the previous accumulation interval. An LCV event is defined as the occurrence of a Bipolar Violation or Excessive Zeros. The counting of Excessive Zeros can be disabled by the BPV bit of the Receive Line Interface Configuration register.
PROPRIETARY AND CONFIDENTIAL
205
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Register 060H: T1 ALMI Configuration Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W R/W R/W
Unused Unused Unused ESF FMS1 FMS0 Unused Unused
X X X 0 0 0 X X
When the E1/T1B bit of the Global Configuration register is a logic 1, this register is held reset. This register allows selection of the framing format and the data rate of the Facility Data Link in ESF to allow operation of the CFA detection algorithms. ESF: The ESF bit selects either extended superframe format or enables the frame mode select bits to select either regular superframe, T1DM, "alternate" T1DM, or SLC(R)96 framing formats. A logic 1 in the ESF bit position selects ESF; a logic 0 bit enables FMS1 and FMS0 to select SF, T1DM, "alternate" T1DM, or SLC(R)96. FMS1,FMS0: The FMS1 and FMS0 bits select standard superframe, T1DM, "alternate" T1DM, or SLC(R)96 framing formats. A logic 00 in these bits enable the SF framing format; a logic 01 in these bit positions enable the T1DM framing format; a logic 10 in these bit positions enable the SLC(R)96 framing format; and a logic 11 in these bit positions enable the "alternate" T1DM framing format. The "alternate" T1DM framing format configures the ALMI to process the Red alarm as if the SF, SLC(R)96, or ESF framing format were selected; the Yellow alarm is still processed as T1DM. When ESF is selected (ESF bit set to logic 1), the FMS1 and FMS0 bits select the data rate and the source channel for the Facility Data Link (FDL) data. A logic 00 in these bits enables the ALMI to receive FDL data and validate the Yellow alarm at the full 4 kbit rate.
PROPRIETARY AND CONFIDENTIAL
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The valid combinations of the ESF, FMS1, and FMS0 bits are summarized in the table below:
Table 42 ESF - T1 Framing Modes FMS1 FMS0 Mode
0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1
Select Superframe framing format Select T1DM framing format Select SLC-96 framing format Select "alternate" T1DM mode Select ESF framing format & 4 kbit FDL Data Rate Reserved Reserved Reserved
PROPRIETARY AND CONFIDENTIAL
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Register 061H: T1 ALMI Interrupt Enable Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W R/W R/W R/W R/W
Unused Unused Unused FASTD ACCEL YELE REDE AISE
X X X 0 0 0 0 0
When the E1/T1B bit of the Global Configuration register is a logic 1, this register is held reset. This register selects which of the three CFA's can generate an interrupt when their logic state changes and enables the "fast" deassertion mode of operation. FASTD: The FASTD bit enables the "fast" deassertion of Red and AIS alarms. When FASTD is set to a logic 1, deassertion of Red alarm occurs within 120 ms of going in frame. Deassertion of AIS alarm occurs within 180 ms of either detecting a 60 ms interval containing 127 or more zeros, or going in frame. When FASTD is set to a logic 0, Red and AIS alarm deassertion times remain as defined in the ALMI description. ACCEL: The ACCEL bit is used for production test purposes only. THE ACCEL BIT MUST BE PROGRAMMED TO LOGIC 0 FOR NORMAL OPERATION. YELE, REDE, AISE: A logic 1 in the enable bit positions (YELE, REDE, AISE) enables a state change in the corresponding CFA to generate an interrupt; a logic 0 in the enable bit positions disables any state changes to generate an interrupt. The enable bits are independent; any combination of Yellow, Red, and AIS CFA's can be enabled to generate an interrupt. Upon reset of the COMET, these bits are cleared to logic 0.
PROPRIETARY AND CONFIDENTIAL
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Register 062H: T1 ALMI Interrupt Status Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R R R R R R
Unused Unused YELI REDI AISI YEL RED AIS
X X 0 0 0 0 0 0
When the E1/T1B bit of the Global Configuration register is a logic 1, this register is held reset. This register indicates which of the three Carry Failure Alarms (CFA's) generated an interrupt when their logic state changed in bit positions 5 through 3, and indicate the current state of each CFA in bit positions 2 through 0. A logic 1 in the status positions (YELI, REDI, AISI) indicate that a state change in the corresponding CFA has generated an interrupt; a logic 0 in the status positions indicates that no state change has occurred. Both the status bit positions (bits 5 through 3) and the interrupt generated because of the change in CFA state are cleared to logic 0 when the register containing then is read.
PROPRIETARY AND CONFIDENTIAL
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Register 063H: T1 ALMI Alarm Detection Status Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R R R
Unused Unused Unused Unused Unused REDD YELD AISD
X X X X X X X X
When the E1/T1B bit of the Global Configuration register is a logic 1, this register is held reset. This register indicates the presence or absence of one or more OOF occurrences within the last 40 ms; the presence or absence of the Yellow alarm signal over the last 40 ms; and indicate the presence or absence of the AIS alarm signal over the last 60 ms. REDD: When REDD is a logic 1, one or more out of frame events have occurred during the last 40 ms interval. When REDD is a logic 0, no out of frame events have occurred within the last 40 ms interval. YELD: When YELD is logic 1, a valid Yellow signal was present during the last 40 ms interval. When YELD is logic 0, the Yellow signal was absent during the last 40 ms interval. For each framing format, a valid Yellow signal is deemed to be present if: bit 2 of each channel is not logic 0 for 16 or fewer times during the 40 ms interval for SF and SLC(R)96 framing formats; the Y-bit is not logic 0 for 4 or fewer times during the 40 ms interval for T1DM framing format; the 16-bit Yellow bit oriented code is received error-free 8 or more times during the interval for ESF framing format with a 4 kHz data link;
PROPRIETARY AND CONFIDENTIAL
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COMBINED E1/T1 TRANSCEIVER
In a Japanese T1 mode, the 12th F-bit toggles between 1 and 0 signifying a Japanese Yellow alarm AISD: When AISD is logic 1, a valid AIS signal was present during the last 60 ms interval. When AISD is logic 0, the AIS signal was absent during the last 60 ms interval. A valid AIS signal is deemed to be present during a 60 ms interval if the out of frame condition has persisted for the entire interval and the received PCM data stream is not logic 0 for 126 or fewer times.
PROPRIETARY AND CONFIDENTIAL
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Register 065H: T1 PDVD Interrupt Enable/Status Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R R R R/W R/W
Unused Unused Unused PDV Z16DI PDVI Z16DE PDVE
X X X 0 0 0 0 0
When the E1/T1B bit of the Global Configuration register is a logic 1, this register is held reset. Also, this register is only available when the RUNI bit in the Receive Line Interface Configuration register is logic 0. PDV: The PDV bit indicates the current state of the pulse density violation indication. When PDV is a logic 1, a violation of the pulse density rule exists. When PDV is a logic 0, no violation of the pulse density rule exists. Note: the PDV indication persists for the duration of the pulse density violation. At its minimum, PDV may be asserted for only 1 bit time, therefore, reading this bit may not return a logic 1 even though a pulse density violation has occurred. PDVI, Z16DI: The PDVI and Z16DI bits identify the source of a generated interrupt. PDVI is a logic 1 whenever a change in the pulse density violation indication generated an interrupt. PDVI is cleared to 0 when this register is read. Z16DI is a logic 1 whenever 16 consecutive zeros are detected. Z16DI is cleared to 0 when this register is read. Note that the PDVI and Z16DI interrupt indications operate regardless of whether interrupts are enabled or disabled. Z16DE: The Z16DE bit enables an interrupt to be generated on the microprocessor INTB pin when 16 consecutive zeros are detected. When Z16DE is set to logic 1, interrupt is generation is enabled. When Z16DE is set to logic 0, interrupt generation is disabled.
PROPRIETARY AND CONFIDENTIAL
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PDVE: The PDVE bit enables an interrupt to be generated on the microprocessor INTB pin when a change in the pulse density is detected. When PDVE is set to logic 1, an interrupt is generated whenever a pulse density violation occurs or when the pulse density ceases to exist. When PDVE is set to logic 0, interrupt generation by pulse density violations is disabled.
PROPRIETARY AND CONFIDENTIAL
213
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Register 067H: T1 XBOC Code Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W R/W R/W R/W R/W R/W
Unused Unused BC[5] BC[4] BC[3] BC[2] BC[1] BC[0]
X X 1 1 1 1 1 1
When the E1/T1B bit of the Global Configuration register is a logic 1, this register is held reset. This register enables the XBOC to generate a bit oriented code and selects the 6-bit code to be transmitted. When this register is written with any 6-bit code other than 111111, that code will be transmitted repeatedly in the ESF Facility Data Link with the format 111111110[BC0][BC1][BC2][BC3][BC4][BC5]0, overwriting any HDLC packets currently being transmitted. When the register is written with 111111, the XBOC is disabled.
PROPRIETARY AND CONFIDENTIAL
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Register 069H: T1 XPDE Interrupt Enable/Status Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
R/W R/W R R R R R/W R/W
STUFE STUFF STUFI PDV Z16DI PDVI Z16DE PDVE
0 0 0 0 0 0 0 0
When the E1/T1B bit of the Global Configuration register is a logic 1, this register is held reset. STUFE: The STUFE bit enables the occurrence of pulse stuffing to generate an interrupt on INTB. When STUFE is set to logic 1, an interrupt is generated on the occurrence of a bit stuff. When STUFE is a logic 0, bit stuffing occurrences do not generate an interrupt on INTB. STUFF: The STUFF bit enables pulse stuffing to occur upon detection of a violation of the pulse density rule. Bit stuffing is performed in such a way that the resulting data stream no longer violates the pulse density rule. When STUFF is set to logic 1, bit stuffing is enabled and the STUFI bit indicates the occurrence of bit stuffs. When STUFF is a logic 0, bit stuffing is disabled and the PDVI bit indicates occurrences of pulse density violation. Also, when STUFF is a logic 0, PCM data passes through XPDE unaltered. STUFI: The STUFI bit is valid when pulse stuffing is active. This bit indicates when a bit stuff occurred to eliminate a pulse density violation and that an interrupt was generated due to the bit stuff (if STUFE is logic 1). When pulse stuffing is active, PDVI remains logic 0, indicating that the stuffing has removed the density violation. The STUFI bit is reset to logic 0 once this register is read. If the STUFE bit is also logic 1, the interrupt is also cleared once this register is read.
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PDV: The PDV bit indicates the current state of the pulse density violation indication. When PDV is a logic 1, a violation of the pulse density rule exists. When PDV is a logic 0, no violation of the pulse density rule exists. Note: the PDV indication persists for the duration of the pulse density violation. At its minimum, PDV may be asserted for only 1 bit time, therefore, reading this bit may not return a logic 1 even though a pulse density violation has occurred. When the XPDE is enabled for pulse stuffing, PDV remains logic 0. PDVI, Z16DI: The PDVI and Z16DI bits identify the source of a generated interrupt. PDVI is a logic 1 whenever a change in the pulse density violation indication generated an interrupt. PDVI is cleared to 0 when this register is read. Z16DI is a logic 1 whenever 16 consecutive zeros are detected. Z16DI is cleared to 0 when this register is read. Note that the PDVI and Z16DI interrupt indications operate regardless of whether the corresponding interrupt enables are enabled or disabled. When STUFF is set to logic 1, the PDVI and Z16DI bits are forced to logic 0. Z16DE: The Z16DE bit enables an interrupt to be generated on the microprocessor INTB pin when 16 consecutive zeros are detected. When Z16DE is set to logic 1, interrupt is generation is enabled. When Z16DE is set to logic 0, interrupt generation is disabled. PDVE: The PDVE bit enables an interrupt to be generated on the microprocessor INTB pin when a change in the pulse density is detected. When PDVE is set to logic 1, an interrupt is generated whenever a pulse density violation occurs or when the pulse density ceases to exist (if STUFE is logic 0). When PDVE is set to logic 0, interrupt generation by pulse density violations is disabled.
PROPRIETARY AND CONFIDENTIAL
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Register 06AH: T1 RBOC Enable Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W R/W R/W
Unused Unused Unused Unused Unused IDLE AVC BOCE
X X X X X 0 0 0
When the E1/T1B bit of the Global Configuration register is a logic 1, this register is held reset. This register selects the validation criteria to be used in determining a valid bit oriented code (BOC) and enables generation of an interrupt on a change in code status. IDLE: The IDLE bit position enables or disables the generation of an interrupt when there is a transition from a validated BOC to idle code. A logic 1 in this bit position enables generation of an interrupt; a logic 0 in this bit position disables interrupt generation. AVC: The AVC bit position selects the validation criteria used in determining a valid BOC. A logic 1 in the AVC bit position selects the "alternate" validation criterion of 4 out of 5 matching BOCs; a logic 0 selects the 8 out of 10 matching BOC criterion. BOCE: The BOCE bit position enables or disables the generation of an interrupt on the microprocessor INTB pin when a valid BOC is detected. A logic 1 in this bit position enables generation of an interrupt; a logic 0 in this bit position disables interrupt generation.
PROPRIETARY AND CONFIDENTIAL
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Register 06BH: T1 RBOC Code Status Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
R R R R R R R R
IDLEI BOCI BOC[5] BOC[4] BOC[3] BOC[2] BOC[1] BOC[0]
0 0 1 1 1 1 1 1
When the E1/T1B bit of the Global Configuration register is a logic 1, this register is held reset. BOC[5:0]: The BOC[5:0] bits indicate the current state value of the received bit-oriented code. IDLEI: The IDLEI bit position indicates whether an interrupt was generated by the detection of the transition from a valid BOC to idle code. A logic 1 in the IDLEI bit position indicates that a transition from a valid BOC to idle code has generated an interrupt; a logic 0 in the IDLEI bit position indicates that no transition from a valid BOC to idle code has been detected. IDLEI is cleared to logic 0 when the register is read. BOCI: The BOCI bit position indicates whether an interrupt was generated by the detection of a valid BOC. A logic 1 in the BOCI bit position indicates that a validated BOC code has generated an interrupt; a logic 0 in the BOCI bit position indicates that no BOC has been detected. BOCI is cleared to logic 0 when the register is read.
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Register 06CH: TPSC Configuration Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W R/W R/W
Unused Unused Unused Unused Unused Reserved IND PCCE
X X X X X 0 0 0
This register allows selection of the microprocessor read access type and output enable control for the Transmit Per-channel Serial Controller. Reserved: The Reserved bit must be programmed to logic 0 for normal operation. IND: The IND bit controls the microprocessor access type: either indirect or direct. The IND bit must be set to logic 1 for proper operation. When the COMET is reset, the IND bit is set low, disabling the indirect access mode. PCCE: The PCCE bit enables the per-channel functions. When the PCCE bit is set to a logic 1, each channel's PCM Control byte, IDLE Code byte, and SIGNALING Control byte are passed on to the XBAS. When the PCCE bit is set to logic 0, the per-channel functions are disabled.
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Register 06DH: TPSC P Access Status Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
R
BUSY Unused Unused Unused Unused Unused Unused Unused
X X X X X X X X
The BUSY bit in the Status register is high while a P access request is in progress. The BUSY bit goes low timed to an internal high-speed clock rising edge after the access has been completed. During normal operation, the Status Register should be polled until the BUSY bit goes low before another P access request is initiated. A P access request is typically completed within 640 ns.
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Register 06EH: TPSC Channel Indirect Address/Control Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
R/W R/W R/W R/W R/W R/W R/W R/W
R/WB A6 A5 A4 A3 A2 A1 A0
0 0 0 0 0 0 0 0
This register allows the P to access the internal TPSC registers addressed by the A[6:0] bits and perform the operation specified by the R/WB bit. Writing to this register with a valid address and R/WB bit initiates an internal P access request cycle. The R/WB bit selects the operation to be performed on the addressed register: when R/WB is set to a logic 1, a read from the internal TPSC register is requested; when R/WB is set to a logic 0, a write to the internal TPSC register is requested.
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Register 06FH: TPSC Channel Indirect Data Buffer Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
R/W R/W R/W R/W R/W R/W R/W R/W
D7 D6 D5 D4 D3 D2 D1 D0
0 0 0 0 0 0 0 0
This register contains either the data to be written into the internal TPSC registers when a write request is initiated or the data read from the internal TPSC registers when a read request has completed. During normal operation, if data is to be written to the internal registers, the byte to be written must be written into this Data register before the target register's address and R/WB=0 is written into the Address/Control register, initiating the access. If data is to be read from the internal registers, only the target register's address and R/WB=1 is written into the Address/Control register, initiating the request. After 640 ns, this register will contain the requested data byte. The internal TPSC registers control the per-channel functions on the Transmit PCM data, provide the per-channel Transmit IDLE Code, and provide the perchannel Transmit signaling control and the alternate signaling bits. The functions are allocated within the registers as follows:
Table 43 Addr - TPSC Indirect Register Map Register
20H 21H 22H
* *
PCM Data Control byte for Timeslot 0 PCM Data Control byte for Channel 1/Timeslot 1 PCM Data Control byte for Channel 2/Timeslot 2
* *
37H 38H
PCM Data Control byte for Channel 23/Timeslot 23 PCM Data Control byte for Channel 24/Timeslot 24
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Addr
Register
39H
* *
PCM Data Control byte for Timeslot 25
* *
3EH 3FH 40H 41H 42H
* *
PCM Data Control byte for Timeslot 30 PCM Data Control byte for Timeslot 31 IDLE Code byte for Timeslot 0 IDLE Code byte for Channel 1/Timeslot 1 IDLE Code byte for Channel 2/Timeslot 2
* *
57H 58H 59H
* *
IDLE Code byte for Channel 23/Timeslot 23 IDLE Code byte for Channel 24/Timeslot 24 IDLE Code byte for Timeslot 25
* *
5EH 5FH 60H 61H 62H
* *
IDLE Code byte for Timeslot 30 IDLE Code byte for Timeslot 31 E1 Control byte for Timeslot 0 Signaling/E1 Control byte for Channel 1/Timeslot 1 Signaling/E1 Control byte for Channel 2/Timeslot 2
* *
77H 78H 79H
* *
Signaling/E1 Control byte for Channel 23/Timeslot 23 Signaling/E1 Control byte for Channel 24/Timeslot 24 Signaling/E1 Control byte for Timeslot 25
* *
7EH 7FH
Signaling/E1 Control byte for Timeslot 30 Signaling/E1 Control byte for Timeslot 31
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The "Timeslot" designation refers to the E1 assignment. The "Channel" designation refers to the T1 assignment. The bits within each control byte are allocated as follows:
Table 44 Bit - TPSC Indirect Registers 20H-3FH: PCM Data Control byte Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 INVERT:
R/W R/W R/W R/W R/W R/W R/W R/W
INVERT IDLE_DS0 DMW SIGNINV TEST LOOP ZCS0 ZCS1
X X X X X X X X
When the INVERT bit is set to a logic 1, data from the BTPCM input is inverted for the duration of that channel. The INVERT bit only has effect in T1 mode. IDLE_DS0: When the IDLE_DS0 bit is set to a logic 1, data from the IDLE Code Byte replaces the BTPCM input data for the duration of that channel. The IDLE_DS0 bit controls insertion of the IDLE Code Byte only in T1 mode. When the NxDS0 mode is active, IDLE_DS0 also controls the generation of BTCLK. When IDLE_DS0 is a logic 0, data is inserted from the transmit backplane interface during that channel, and eight clock pulses are generated on BTCLK. When IDLE_DS0 is a logic 1, an IDLE code byte is inserted, and BTCLK is suppressed for the duration of that channel. SIGNINV: When the SIGNINV bit is set to a logic 1, the most significant bit from the BTPCM input is inverted for that channel. The SIGNINV bit only has effect in T1 mode.
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The INVERT and SIGNINV can be used to produce the following types of inversions:
Table 45 INVERT - TPSC Transmit Data Conditioning SIGNINV Effect on PCM Channel Data
0 1 0 1
0 0 1 1
PCM Channel data is unchanged All 8 bits of the PCM channel data are inverted Only the MSB of the PCM channel data is inverted (SIGN bit inversion) All bits EXCEPT the MSB of the PCM channel data is inverted (Magnitude inversion)
DMW: When the DMW bit is set to a logic 1, the digital milliwatt pattern replaces the BTPCM input data for the duration of that channel. The DMW bit only has effect in T1 mode. TEST: When the TEST bit is set to a logic 1, channel data from the BTPCM input is either overwritten with a test pattern from the PRGD block or is routed to the PRGD block and compared against an expected test pattern. The RXPATGEN bit in the Pattern Generator/Detector Positioning/Control register determines whether the transmit data is overwritten or compared as shown in the following table:
Table 46 TEST - Transmit Test Pattern Modes RXPATGEN Description
0 1 1
X 1 0
Channel data is not included in test pattern Channel data is routed to PRGD and compared against expected test pattern Channel data is overwritten with PRGD test pattern
All the channels that are routed to the PRGD are concatenated and treated as a continuous stream in which pseudorandom are searched for. Similarly, all channels set to be overwritten with PRGD test pattern data are treated such that if the channels are subsequently extracted and concatenated, the PRBS appears in the concatenated stream. Pattern generation/detection can
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be enabled to work on only the first 7 bits of a channel (for Nx56 kbps fractional T1) using the Nx56k_DET and Nx56k_GEN bits in the Pattern Generator/Detector Positioning/Control register. The PRGD can also be enabled to work on the entire DS1, including framing bits, using the UNF_GEN and UNF_DET bits in the Pattern Generator/Detector Positioning/Control register. LOOP: The LOOP bit enables the DS0 loopback. When the LOOP bit is set to a logic 1, transmit data is overwritten with the corresponding channel data from the receive line. When the Receive Elastic Store (RX-ELST) is bypassed, it is used to align the receive line data to the transmit frame. When RX-ELST is enabled, however, it is unavailable to facilitate per-DS0 loopbacks. Data inversion, idle, loopback and test pattern insertion/checking are performed independent of the transmit framing format. DS0 loopback takes precedence over digital milliwatt pattern insertion. Next in priority is test pattern insertion, which, in turn, takes precedence over idle code insertion. Data inversion has the lowest priority. When test pattern checking is enabled, the transmit data is compared before DS0 loopback, digital milliwatt pattern insertion, idle code insertion or data inversion is performed. None of this prioritizing has any effect on the gapping of BTCLK in NxDS0 mode. That is, if both DS0 loopback and idle code insertion are enabled for a given channel while in NxDS0 mode, the DS0 will be looped-back, will not be overwritten with idle code, and BTCLK will be gapped out for the duration of the channel. Similarly, none of the prioritizing has any effect on the generation of test patterns from the PRGD, only on the insertion of that pattern. Thus, if both DMW and TEST are set for a given DS0, and RXPATGEN = 0, the test pattern from the PRGD will be overwritten with the digital milliwatt code. This same rule also applies to test patterns inserted via the UNF_GEN bit in the Pattern Generator/Detector Positioning/Control register. ZCS0, ZCS1: The ZCS0 and ZCS1 bits select the zero code suppression used as follows:
Table 47 ZCS0 - Transmit Zero Code Suppression Formats ZCS1 Description
0 0
0 1
No Zero Code Suppression "Jammed bit 8" - Every bit 8 is forced to a one. This may be used for 56 kbit/s data service. This is the only code that should be inserted in E1 mode.
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ZCS0
ZCS1
Description
1
0
GTE Zero Code Suppression (Bit 8 of an all zero channel byte is replaced by a one, except in signaling frames where bit 7 is forced to a one.) Bell Zero Code Suppression (Bit 7 of an all zero channel byte is replaced by a one.)
- TPSC Indirect Registers 40H-5FH: IDLE Code byte Type Function Default
1
1
Table 48 Bit
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
R/W R/W R/W R/W R/W R/W R/W R/W
IDLE7 IDLE6 IDLE5 IDLE4 IDLE3 IDLE2 IDLE1 IDLE0
X X X X X X X X
The contents of the IDLE Code byte register is substituted for the channel data on BTPCM when the IDLE_DS0 bit in the PCM Control Byte is set to a logic 1 in T1 mode or when the SUBS bit of the E1 Control Byte is logic 1 and the DS[0] bit of the E1 Control Byte is logic 0 in E1 mode. The IDLE Code is transmitted from MSB (IDLE7) to LSB (IDLE0).
Table 49 Bit - TPSC Indirect Registers 60H-7FH: Signaling/E1 Control byte Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1
R/W R/W R/W R/W R/W R/W R/W
SIGC[0]/SUBS SIGC[1]/DS[0] DS[1] SIGSRC A' B' C'
X X X X X X X
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Bit
Type
Function
Default
Bit 0
R/W
D'
X
The significance of the bits in these registers is dependent on whether the operating mode is T1 or E1.
E1 Mode
SUBS, DS[1], and DS[0]: The SUBS, DS[1], and DS[0] bits select one of the following data manipulations to be performed on the timeslot:
Table 50 - Transmit Per-timeslot Data Manipulation DS[1] Function
SUBS DS[0]
0 0 0 0 1 1 1
0 0 1 1 0 1 1
0 1 0 1 X 0 1
OFF - no change to PCM timeslot data ADI - data inversion on timeslot bits 1, 3, 5, 7 ADI - data inversion on timeslot bits 2, 4, 6, 8 INV - data inversion on all timeslot bits Data substitution on - IDLE code replaces BTPCM timeslot data Data substitution on - A-Law digital pattern* replaces BTPCM timeslot data. Data substitution on - -Law digital pattern* replaces BTPCM timeslot data.
*Note: The A-Law digital milliwatt pattern used is that defined in Recommendation G.711 for A-law:
Table 51 Bit 1 - A-Law Digital Milliwatt Pattern Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Bit 8
0 0 0 0
0 0 0 0
1 1 1 1
1 0 0 1
0 0 0 0
1 0 0 1
0 0 0 0
0 1 1 0
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Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Bit 8
1 1 1 1
0 0 0 0
1 1 1 1
1 0 0 1
0 0 0 0
1 0 0 1
0 0 0 0
0 1 1 0
*Note: The -Law digital milliwatt pattern used is that defined in Recommendation G.711 for -law:
Table 52 Bit 1 - -Law Digital Milliwatt Pattern Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Bit 8
0 0 0 0 1 1 1 1 SIGSRC:
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
1 0 0 1 1 0 0 1
1 1 1 1 1 1 1 1
1 0 0 1 1 0 0 1
1 1 1 1 1 1 1 1
0 1 1 0 0 1 1 0
The SIGSRC bit is valid only if Channel Associated Signaling (CAS) is selected in the E1-TRAN Configuration Register; otherwise, it is ignored. When valid, the SIGSRC bit selects the source of the timeslot signaling bits: if SIGSRC is a logic 0, the signaling bits are taken from the incoming BTSIG stream in the format specified by the SIGEN and DLEN bits in the E1-TRAN Configuration Register; if SIGSRC is a logic 1, the signaling bits are taken from the A',B',C', and D' bit .
T1 Mode
Signaling insertion is controlled by the SIGC[1:0] bits. The source of the signaling bits is determined by SIGC0: when SIGC0 is set to a logic 1, signaling data is taken from the A', B', C', and D' bits; when SIGC0 is set to logic 0, signaling data is taken from the A,B,C, and D bit locations on the BTSIG input. Signaling insertion is controlled by SIGC1: when SIGC1 is set to a logic 1 and
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ESF, SF, or SLC(R)96 transmit format is selected, insertion of signaling bits is enabled; when SIGC1 is set to logic 0, the insertion of signaling bits is disabled. For SF and SLC(R)96 formats, the C' and D' or C and D bits from Signaling Control byte or BTSIG, respectively, are inserted into the A and B signaling bit positions of every second superframe that is transmitted. It is assumed that C=A and D=B. The A',B',C', and D' bits do not pass through the Signaling Aligner block. When signaling insertion via the A',B',C', and D' bits is enabled, changing the signaling state by writing to the TPSC can cause the transmit stream to briefly (for one superframe or extended superframe) carry a signaling state that is neither the new or the old signaling state (e.g., may have the A bit from the new state but the B bit from the old state).
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Register 070H: RPSC Configuration Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W R/W R/W
Unused Unused Unused Unused Unused Reserved IND PCCE
X X X X X 0 0 0
This register allows selection of the microprocessor read access type and output enable control for the Receive Per-channel Serial Controller. Reserved: The Reserved bit must be programmed to logic 0 for normal operation. IND: The IND bit controls the microprocessor access type: either indirect or direct. The IND bit must be set to logic 1 for proper operation. When the COMET is reset, the IND bit is set low, disabling the indirect access mode. PCCE: The PCCE bit enables the per-channel functions. When the PCCE bit is set to a logic 1, the Data Trunk Conditioning Code byte and Signaling Trunk Conditioning Code byte are enabled to modify the received data and extracted signaling data streams (visible on BRPCM and BRSIG, if selected) under direction of each channel's PCM Control byte. When the PCCE bit is set to logic 0, the per-channel functions are disabled.
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Register 071H: RPSC P Access Status Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
R
BUSY Unused Unused Unused Unused Unused Unused Unused
X X X X X X X X
The BUSY bit in the Status register is high while a P access request is in progress. The BUSY bit goes low timed to an internal high-speed clock rising edge after the access has been completed. During normal operation, the Status Register should be polled until the BUSY bit goes low before another P access request is initiated. A P access request is typically completed within 640 ns.
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Register 072H: RPSC Channel Indirect Address/Control Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
R/W R/W R/W R/W R/W R/W R/W R/W
R/WB A6 A5 A4 A3 A2 A1 A0
0 0 0 0 0 0 0 0
This register allows the P to access the internal RPSC registers addressed by the A[6:0] bits and perform the operation specified by the R/WB bit. Writing to this register with a valid address and R/WB bit initiates an internal P access request cycle. The R/WB bit selects the operation to be performed on the addressed register: when R/WB is set to a logic 1, a read from the internal RPSC register is requested; when R/WB is set to a logic 0, an write to the internal RPSC register is requested.
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Register 073H: RPSC Channel Indirect Data Buffer Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
R/W R/W R/W R/W R/W R/W R/W R/W
D7 D6 D5 D4 D3 D2 D1 D0
0 0 0 0 0 0 0 0
This register contains either the data to be written into the internal RPSC registers when a write request is initiated or the data read from the internal RPSC registers when a read request has completed. During normal operation, if data is to be written to the internal registers, the byte to be written must be written into this Data register before the target register's address and R/WB=0 is written into the Address/Control register, initiating the access. If data is to be read from the internal registers, only the target register's address and R/WB=1 is written into the Address/Control register, initiating the request. After 640 ns, this register will contain the requested data byte. The internal RPSC registers control the per-channel functions on the Receive PCM data provide the per-channel Data Trunk Conditioning Code and provide the per-channel Signaling Trunk Conditioning Code. The functions are allocated within the registers shown in Table 53:
Table 53 Addr - RPSC Indirect Register Map Register
20H 21H 22H
* *
PCM Data Control byte for Timeslot 0 PCM Data Control byte for Channel 1/Timeslot 1 PCM Data Control byte for Channel 2/Timeslot 2
* *
37H 38H
PCM Data Control byte for Channel 23/Timeslot 23 PCM Data Control byte for Channel 24/Timeslot 24
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Addr
Register
39H
* *
PCM Data Control byte for Timeslot 25
* *
3EH 3FH 40H 41H 42H
* *
PCM Data Control byte for Timeslot 30 PCM Data Control byte for Timeslot 31 Data Trunk Conditioning byte for Timeslot 0 Data Trunk Conditioning byte for Channel 1/Timeslot 1 Data Trunk Conditioning byte for Channel 2/Timeslot 2
* *
57H 58H 59H
* *
Data Trunk Conditioning byte for Channel 23/Timeslot 23 Data Trunk Conditioning byte for Channel 24/Timeslot 24 Data Trunk Conditioning byte for Timeslot 25
* *
5EH 5FH 61H 62H
* *
Data Trunk Conditioning byte for Timeslot 30 Data Trunk Conditioning byte for Timeslot 31 Signaling Trunk Conditioning byte for Channel 1/Timeslot 1 Signaling Trunk Conditioning byte for Channel 2/Timeslot 2
* *
77H 78H 79H
* *
Signaling Trunk Conditioning byte for Channel 23/Timeslot 23 Signaling Trunk Conditioning byte for Channel 24/Timeslot 24 Signaling Trunk Conditioning byte for Timeslot 25
* *
7EH 7FH
Signaling Trunk Conditioning byte for Timeslot 30 Signaling Trunk Conditioning byte for Timeslot 31
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The "Timeslot" designation refers to the E1 assignment. The "Channel" designation refers to the T1 assignment. The bits within each control byte are allocated as follows:
Table 54 Bit - RPSC Indirect Registers 20H-3FH: PCM Data Control byte Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TEST:
R/W R/W R/W R/W R/W R/W
TEST DTRKC STRKC DMW DMWALAW SIGNINV Unused Unused
X X X X X X X X
When the TEST bit is set to a logic 1, receive channel data is either overwritten with a test pattern from the PRGD block or is routed to the PRGD block and compared against an expected test pattern. The RXPATGEN bit in the Pattern Generator/Detector Positioning/Control register determines whether the transmit data is overwritten or compared as shown in the following table:
Table 55 TEST - Receive Test Pattern Modes RXPATGEN Description
0 1 1
X 0 1
Channel data is not included in test pattern Channel data is routed to PRGD and compared against expected test pattern Channel data is overwritten with PRGD test pattern
All the channels that are routed to the PRGD are concatenated and treated as a continuous stream in which pseudorandom are searched for. Similarly, all channels set to be overwritten with PRGD test pattern data are treated such that if the channels are subsequently extracted and concatenated, the PRBS appears in the concatenated stream. Pattern generation/detection can be enabled to work on only the first 7 bits of a channel (for Nx56 kbps fractional T1) using the
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Nx56k_DET and Nx56k_GEN bits in the Pattern Generator/Detector Positioning/Control register. The PRGD can also be enabled to work on the entire DS1, including framing bits, using the UNF_GEN and UNF_DET bits in the Pattern Generator/Detector Positioning/Control register. DTRKC: When the DTRKC bit is set to a logic 1, data from the Data Trunk Conditioning Code Byte contained within the RPSC indirect registers replaces the BRPCM output data for the duration of that channel. When the Receive Backplane Configuration register selects a NxDS0 mode, the DTRKC bit also controls BRCLK generation. If DTRKC is a logic 1, BRCLK is held low for the duration of the channel. STRKC: When the STRKC bit is set to a logic 1, data from the Signaling Trunk Conditioning Code Byte contained within the RPSC indirect registers replaces the BRSIG output data for the duration of that channel. DMW: When the DMW bit is set to a logic 1, a digital milliwatt pattern replaces the BRPCM output data for the duration of that channel. The particular digital milliwatt pattern used, A-law or u-law, is selected by the DMWALAW bit of this register. DMWALAW: When the DMWALAW bit is set to a logic 1, the digital milliwatt pattern replacing the BRPCM output data for the duration of that channel is the A-law pattern (see Table 51). When the DMWALAW bit is set to a logic 0, the digital milliwatt pattern replacing the BRPCM output data for the duration of that channel is the -law pattern (see Table 52). SIGNINV: When the SIGNINV bit is set to a logic 1, the most significant bit of the data output on the BRPCM pin is the inverse of the received data most significant bit for that channel. In T1 mode, the RINV[1] of the and SIGNINV bits can be used to invert data as shown in Table 37:
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Table 56 Code byte Bit
- RPSC Indirect Registers 40H-5FH: Data Trunk Conditioning Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
R/W R/W R/W R/W R/W R/W R/W R/W
DTRK7 DTRK6 DTRK5 DTRK4 DTRK3 DTRK2 DTRK1 DTRK0
X X X X X X X X
The contents of the Data Trunk Conditioning Code byte register is substituted for the channel data on BRPCM when the DTRKC bit in the PCM Control Byte is set to a logic 1. The Data Trunk Conditioning Code is transmitted from MSB (DTRK7) to LSB (DTRK0).
Table 57 - RPSC Indirect Registers 61H-7FH: Signaling Trunk Conditioning byte Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W R/W R/W R/W
Unused Unused Unused Unused A' B' C' D'
X X X X X X X X
The contents of the Signaling Trunk Conditioning Code byte register is substituted for the channel signaling data on BRSIG when the STRKC bit is set to a logic 1. The Signaling Trunk Conditioning Code is placed in least significant nibble of the channel byte.
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Register 078H: T1 APRM Configuration/Control Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W R/W R/W R/W R/W R/W
Unused Unused R U1 U2 CONT_CRC INTE AUTOUPDATE
X X 0 0 0 0 0 0
AUTOUPDATE: The AUTOUPDATE bit controls the automatic updating of the performance report on a per second basis. If this bit is set to a logic 1, the Performance Report Messages are generated and updated once a second. When AUTOUPDATE is set to a logic 0, the performance report is updated manually by toggling the MAN_LOAD register bit. INTE: The INTE bit enables the interrupt output pin. When INTE is set to a logic 1, a logic 1 in the INTR bit in the T1 APRM Interrupt Status register asserts the INTB output low. INTR is disabled from generating interrupts when INTE is set to a logic 0. CONT_CRC: The CONT_CRC is the Continuous CRC bit. When set to logic 1, the SE and G6 bits in the Performance Report are set to1 and G1, G2, G3, G4, G5 and FE are set to 0. When reset to logic 0, the Gn (n = [1..5]), FE and SE bits are set according to the received CRC errors. U1, U2: The U1, U2 bits are under study for synchronization. Their default value is 0. These bits require two updating cycles before they are included in the performance report.
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R: The R bit is a reserved bit in the performance report. The default value is 0. This bit requires two updating cycles before it is included in the performance report.
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Register 079H: T1 APRM Manual Load Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 MAN_LOAD: R/W
Unused Unused Unused Unused Unused Unused Unused MAN_LOAD
X X X X X X X 0
The MAN_LOAD bit is used to load the next Performance Report into the holding registers. This bit is enabled when AUTOUPDATE is set to a logic 0. In manual PR generation mode, it is important to poll the MAN_LOAD bit to ensure that the previous Performance Report transmission has been transmitted. When the microprocessor requests a Performance Report, the MAN_LOAD bit is set high. When the last bit of the Performance Report has been transmitted, the MAN_LOAD bit is reset to a logic 0.
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Register 07AH: T1 APRM Interrupt Status Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 INTR: R
Unused Unused Unused Unused Unused Unused Unused INTR
X X X X X X X 0
The interrupt (INTR) bit is set to logic 1 on one second boundaries, to signal that the one second data is ready. If the INTE bit is a logic 1, the INTB output is asserted low when INTR is logic 1. INTR is cleared when this register is read.
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Register 07BH: T1 APRM One Second Content Octet 2 Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SAPI[5:0]:
R/W R/W R/W R/W R/W R/W R/W R/W
SAPI[5] SAPI[4] SAPI[3] SAPI[2] SAPI[1] SAPI[0] C/R EA
0 0 1 1 1 0 0 0
The SAPI[5:0] represent the service access point identifier bits. The value of SAPI[5:0] in the performance report is constant i.e., SAPI = 14. C/R: The C/R bit is the Command/Response bit. The value of C/R from the CI is set to a logic 0 and the value of the C/R bit from the carrier is set to a logic 1. EA: The EA bit is the Extended Address bit in the second octet. The EA bit defaults to logic 0.
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Register 07CH: T1 APRM One Second Content Octet 3 Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TEI[6:0]:
R/W R/W R/W R/W R/W R/W R/W R/W
TEI[6] TEI[5] TEI[4] TEI[3] TEI[2] TEI[1] TEI[0] EA
0 0 0 0 0 0 0 1
The TEI[6:0] bits represent the terminal endpoint identifier. The TEI[6:0] default to logic 0. EA: The EA bit is the Extended Address bit in the third octet. The EA bit defaults to logic 1.
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Register 07DH: T1 APRM One Second Content Octet 4 Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
R/W R/W R/W R/W R/W R/W R/W R/W
CONTROL[7] CONTROL[6] CONTROL[5] CONTROL[4] CONTROL[3] CONTROL[2] CONTROL[1] CONTROL[0]
0 0 0 0 0 0 1 1
CONTROL[7:0]: This register set the value of the CONTROL field in the performance report and defaults to "00000011". It is inserted into the fourth octet of the performance report.
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Register 07EH: T1 APRM One Second Content MSB (Octet 5) Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
R R R R R R R R
G3 LV G4 U1 U2 G5 SL G6
X X X X X X X X
The contents of this register represent the values encoded in the latest performance report transmitted. This register is updated coincident with the assertion of the INTR bit of the T1 APRM Interrupt Status register. G3: This bit is set to a logic-1, if the number of CRC error events in a one second interval is greater than 5 and less than or equal to 10 (i.e., 5 < CRC error events 10). LV: This bit is set to a logic 1, if the number of Line code violation events in a one second interval is greater than or equal to 1 (i.e., LCV 1). G4: This bit is set to a logic 1, if the number of CRC error events in a one second interval is greater than 10 and less than or equal to 100 (i.e., 10 PROPRIETARY AND CONFIDENTIAL
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SL: This bit is set to a logic 1 if, one or more controlled slip events occur in a one second interval i.e. (SL 1). G6: This bit is set to a logic 1 if the number of CRC error events in a one second interval is greater than or equal to 320 (i.e., CRC error events 320).
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Register 07FH: T1 APRM One Second Content LSB (Octet 6) Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
R R R R R R R R
FE SE LB G1 R G2 Nm NI
X X X X X X X X
The contents of this register represent the values encoded in the latest performance report transmitted. This register is updated coincident with the assertion of the INTR bit of the T1 APRM Interrupt Status register. FE: This bit is set to a logic 1 if one or more Frame Synchronization Bit Error Event occurs in a 1 second window (SE =0). If more than one FE occurs in a 3 ms window, a SE is declared and the FE bit is set to 0. SE: This bit is set to a logic 1 if, Severely Errored Framing Event 1 (FE =0). If more than one FE occurs in a 3 ms window, a SE is declared and the FE bit is set to 0. LB: This bit is set to a logic 1 if the Payload Loopback is activated. G1: This bit is set to a logic 1 if the number of CRC error events in a one second interval is equal to 1 (i.e., CRC error events =1). R: Reserved. The default value is set by the R bit in the T1 APRM configuration register (register 078H).
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G2: This bit is set to a logic 1 if the number of CRC error events in a one second interval is greater than 1 and less than or equal to 5 (i.e., 1 Table 58 NmNi - NmNi Settings Time
00 11 10 01
t (most recent second) t-1 t-2 t-3
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Register 080H: E1 TRAN Configuration Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
R/W R/W R/W R/W R/W R/W R/W R/W
AMI SIGEN DLEN GENCRC FDIS FEBEDIS INDIS XDIS
0 1 1 0 0 0 0 0
When the E1/T1B bit of the Global Configuration register is a logic 0, this register is held reset. AMI: The AMI bit enables AMI line coding when set to logic 1; when it is set to logic 0, the HDB3 line coding is enabled. SIGEN, DLEN: The SIGEN and DLEN bits select the signaling data source for Time Slot 16 (TS16) as follows:
Table 59 SIGEN - E1 Signaling Insertion Mode DLEN MODE
0 0 1 1
0 1 0 1
Signaling insertion disabled. TS16 data is taken directly from the input BTPCM TS16. Reserved. Reserved. CAS enabled. TS16 data is taken from either BTSIG stream or from the TPSC SIGNALING/E1 Control byte as selected on a per-timeslot basis via the SIGSRC bit. The format of the BTSIG input data stream is shown in the "Functional Timing" section.
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When channel associated signaling (CAS) is enabled, the format of the input BTSIG stream is selected by the DLEN bit. A logic 1 in the DLEN bit position selects the PMC compatible format in which the BTSIG stream contains the signaling data nibble in the lower four bits of the time slot byte. A logic 0 in the DLEN bit position is reserved and should not be used. GENCRC: The GENCRC bit enables generation of the CRC multiframe when set to logic 1. When enabled, the E1-TRAN generates the CRC multiframe alignment signal, calculates and inserts the CRC bits, and if enabled by FEBEDIS, inserts the FEBE indication in the spare bit positions. The CRC bits transmitted during the first submultiframe (SMF) are indeterminate and th should be ignored. The CRC bits calculated during the transmission of the n SMF (SMF n) are transmitted in the following SMF (SMF n+1). When GENCRC is set to logic 0, the CRC generation is disabled. The CRC bits are then set to the logic value contained in the Si[1] bit position in the International/National Bit Control Register and bit 1 of the NFAS frames are set to the value of Si[0] bit if enabled by INDIS, or, if not enabled by INDIS, are taken directly from BTPCM. When BTPCM or Si[1] are transmitted in lieu of the calculated CRC bits, there is no delay of one SMF (i.e., the BTPCM bits received in SMF n are transmitted in the same SMF). The same applies when substituting Si[1] in place of the calculated CRC bits. FDIS: The FDIS bit value controls the generation of the framing alignment signal. A logic 1 in the FDIS bit position disables the generation of the framing pattern in TS0 and allows the incoming data on BTPCM to pass through the E1-TRAN transparently. A logic 0 in FDIS enables the generation of the framing pattern, replacing TS0 of frames 0, 2, 4, 6, 8, 10, 12 and 14 with the frame alignment signal, and if enabled by INDIS, replacing TS0 of frames 1, 3, 5, 7, 9, 11, 13 and 15 with the contents of the International Bits Control Register. When FDIS is a logic 1, framing is globally disabled and the values in control bits GENCRC, FEBEDIS, INDIS, and XDIS are ignored. Note that the above is true only if the AIS bit in the E1-TRAN Transmit Alarm/Diagnostic Control register is a logic 0. If AIS is logic 1, the output bit stream becomes all-ones unconditionally. INDIS, GENCRC and FEBEDIS: The INDIS bit controls the insertion of the International and National bits into TS0. When INDIS is set to logic 0, the contents of the E1-TRAN International Bits Control register and the National bits are inserted into TS0 (note that only the national bits that are enabled in the E1-TRAN National Bits Codeword registers are inserted into TS0); when INDIS is a logic 1, the contents of the
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E1-TRAN International Bits Control register and the E1-TRAN National bits are ignored and the values for those bit positions in the output stream are taken directly from the BTPCM stream. When INDIS and FDIS are logic 0, the bit values used for the International and National bits are dependent upon the values of the GENCRC and FEBEDIS configuration bits, as shown in the following table:
Table 60 GENCRC - E1 Timeslot 0 Bit 1 Insertion Control Summary FEBEDIS Source of International Bits
0
X
Bit position Si[1] in the International Bits Control register is used for the International bit in the frame alignment signal (FAS) frames and the Si[0] bit in the non-frame alignment signal (NFAS) frames if INDIS is logic 0. BTPCM replaces Si[1:0] if INDIS is logic 1. The calculated CRC bits are used for the International bit in the FAS frames and the generated CRC multiframe alignment signal and the FEBE bits are used for the International bit in the NFAS frames. The calculated CRC bits are used for the International bit in the FAS frames and the generated CRC multiframe alignment signal is used for the International bit in the NFAS frames, with the Si[1:0] bits in the International Bits Control register used for the spare bits.
1
0
1
1
XDIS: If FDIS is logic 0 and SIGEN is logic 1, the XDIS bit controls the insertion of the Extra bits in TS16 of frame 0 of the signaling multiframe as follows. When XDIS is set to a logic 0, the contents of the E1-TRAN Extra Bits Control Register are inserted into TS16, frame 0; when XDIS is a logic 1, the contents of the register are ignored and the values for those bits positions in the output stream are taken directly from the BTPCM stream. That is, when XDIS and FDIS are logic 0 and SIGEN is logic 1, the X1, X3 and X4 bit values from the E1-TRAN Extra Bits Control Register are used for the Extra bits in TS16 of frame 0 of the signaling multiframe. When the COMET is reset, the contents of this register are set to logic 0, except SIGEN and DLEN which are set to logic 1.
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Register 081H: E1 TRAN Transmit Alarm/Diagnostic Control Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
R/W R/W R/W R/W R/W R/W R/W R/W
MTRK FPATINV SPLRINV SPATINV RAI YBIT Reserved AIS
0 0 0 0 0 0 0 0
When the E1/T1B bit of the Global Configuration register is a logic 0, this register is held reset. MTRK: The MTRK bit forces trunk conditioning (i.e., idle code substitution and signaling substitution) when MTRK is a logic 1. This has the same effect as setting data substitution to IDLE code on time slots 1-15 and 17-31 (setting bits SUBS and DS[0] to binary 10 in time slots 1-15 and 17-31) and sourcing the signaling data from the TPCS stream, if SIGEN is logic 1. When SIGEN is logic 0, TS16 will be treated the same as time slots 1-15 and 17-31 and will contain data sourced from TIDL. TS0 data is determined by the control bits associated with it and is independent of the value of MTRK. FPATINV: The FPATINV bit is a diagnostic control bit. When set to logic 1, FPATINV forces the frame alignment signal (FAS) written into TS0 to be inverted (i.e., the correct FAS, 0011011, is substituted with 1100100); when set to logic 0, the FAS is unchanged. SPLRINV: The SPLRINV bit is a diagnostic control bit. When set to logic 1, SPLRINV forces the "spoiler bit" written into bit 2 of TS0 of NFAS frames to be inverted (i.e., the spoiler bit is forced to 0); when set to logic 0, the spoiler bit is unchanged.
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SPATINV: The SPATINV bit is a diagnostic control bit. When set to logic 1, SPATINV forces the signaling multiframe alignment signal written into bits 1-4 of TS16 of frame 0 of the signaling multiframe to be inverted (i.e., the correct signaling multiframe alignment signal, 0000, is substituted with 1111); when set to logic 0, the signaling multiframe alignment signal is unchanged. RAI: The RAI bit controls the transmission of the Remote Alarm Indication signal. A logic 1 in the RAI bit position causes bit 3 of NFAS frames to be forced to logic 1; otherwise, bit 3 of NFAS frames is a logic 0 unless the AUTOYELLOW register bit is set and a receive defect is present. YBIT: The YBIT bit controls the transmission of the signaling multiframe Alarm Indication Signal. A logic 1 in the YBIT bit position causes the Y-bit (bit 6) of TS16 of frame 0 of the signaling multiframe to be forced to logic 1; otherwise, the Y-bit is a logic 0. Reserved: This bit must be set to a logic 0 for correct operation. AIS: The AIS bit controls the transmission of the Alarm Indication Signal (unframed all-ones). A logic 1 in the AIS bit position forces the output streams to logic 1. When the COMET is reset, the contents of this register are set to logic 0.
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Register 082H: E1 TRAN International/National Control Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
R/W R/W
Si[1] Si[0] Unused Unused Unused Unused Unused Unused
1 1 X X X X X X
When the E1/T1B bit of the Global Configuration register is a logic 0, this register is held reset. Si[1:0]: The bits Si[1] and Si[0] correspond to the International bits. The Si[1] and Si[0] bits can be programmed to any value and will be inserted into bit 1 of each FAS frame and NFAS frame, respectively, when the block is configured for frame generation, INDIS is set to logic 0, and CRC multiframe generation is disabled. When CRC multiframe generation is enabled, both Si[1] and Si[0] are ignored if FEBE indication is enabled; if FEBEDIS is a logic 1 and INDIS = 0, the values programmed in the Si[1] and Si[0] bit positions are inserted into the spare bit locations of frame 13 and frame 15, respectively, of the CRC multiframe. If both FEBEDIS and INDIS are logic 1, data from BTPCM replaces the Si[0] and Si[1] bits in the CRC multiframe. The Si[1] and Si[0] bits should be programmed to a logic 1 when not being used to carry information. When the COMET is reset, the contents of the register are set to logic 1.
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Register 083H: E1 TRAN Extra Bits Control Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W R/W R/W
Unused Unused Unused Unused X[1] Unused X[3] X[4]
X X X X 1 X 1 1
When the E1/T1B bit of the Global Configuration register is a logic 0, this register is held reset. X[4:3,1]: The X[1], X[3], and X[4] bits control the value programmed in the X[1], X[3], and X[4] bit locations (bits 5,7, and 8) in TS16 of frame 0 of the signaling multiframe, when enabled by XDIS. The X[1], X[3], and X[4] bits should be programmed to a logic 1 when not being used to carry information. When the COMET is reset, the contents of the register are set to logic 1.
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Register 084H: E1 TRAN Interrupt Enable Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W R/W R/W R/W R/W
Unused Unused Unused SIGMFE NFASE MFE SMFE FRME
X X X 0 0 0 0 0
When the E1/T1B bit of the Global Configuration register is a logic 0, this register is held reset. FRME: When FRME is set to logic 1, the interrupt generated by the FRMI interrupt register is propagated to the INTB output pin. When FRME is set to logic 0, the FRMI interrupt bit is masked. SMFE: When SMFE is set to logic 1, the interrupt generated by the SMFI interrupt register is propagated to the INTB output pin. When SMFE is set to logic 0, the SMFI interrupt bit is masked. MFE: When MFE is set to logic 1, the interrupt generated by the MFI interrupt register is propagated to the INTB output pin. When MFE is set to logic 0, the MFI interrupt bit is masked. NFASE: When NFASE is set to logic 1, the interrupt generated by the NFASI interrupt register is propagated to the INTB output pin. When NFASE is set to logic 0, the NFASI interrupt bit is masked.
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SIGMFE: When SIGMFE is set to logic 1, the interrupt generated by the SIGMFI interrupt register is propagated to the INTB output pin. When SIGMFE is set to logic 0, the SIGMFI interrupt bit is masked.
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Register 085H: E1 TRAN Interrupt Status Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R R R R R
Unused Unused Unused SIGMFI NFASI MFI SMFI FRMI
X X X X X X X X
When the E1/T1B bit of the Global Configuration register is a logic 0, this register is held reset. FRMI: The FRMI interrupt bit is set to logic 1 on frame boundaries, it is set on timeslot 30, bit 7 of every frame in the transmit data stream. The contents of this register are cleared to logic 0 after the register is read. SMFI: The SMFI interrupt bit is set to logic 1 on CRC-4 sub multiframe boundaries, it is set on timeslot 30, bit 7 of frame 0 of the CRC submultiframe in the transmit data stream. The contents of this register are cleared to logic 0 after the register is read. MFI: The MFI interrupt bit is set to logic 1 on CRC-4 multiframe boundaries, it is set on timeslot 30, bit 7 of frame 0 of the CRC multiframe in the transmit data stream. The contents of this register are cleared to logic 0 after the register is read. NFASI: The NFASI interrupt bit is set to logic 1 on NFAS frame boundaries, it is set on timeslot 30, bit 7 of the NFAS frame in the transmit data stream. The contents of this register are cleared to logic 0 after the register is read.
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SIGMFI: The SIGMFI interrupt bit is set to logic 1 on signaling multiframe boundaries, it is set on timeslot 14, bit 1 of frame 0 of the signaling multiframe in the transmit data stream. The contents of this register are cleared to logic 0 after the register is read.
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Register 086H: E1 TRAN National Bits Codeword Select Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
R/W R/W R/W
SaSEL[2] SaSEL[1] SaSEL[0] Unused Unused Unused Unused Unused
X X X X X X X X
When the E1/T1B bit of the Global Configuration register is a logic 0, this register is held reset. SaSEL[2:0]: The SaSEL[2:0] bits select which National Bit codeword appears in the SaX[1:4] bits of the E1-TRAN National Bits Codeword register. These bits map to the codeword selection as follows:
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Table 61
- National Bits Codeword Select SaSEL[2:0] National Bit Codeword
000 001 010 011 100 101 110 111
Undefined Undefined Undefined Sa4 Sa5 Sa6 Sa7 Sa8
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Register 087H: E1 TRAN National Bits Codeword Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
R/W R/W R/W R/W R/W R/W R/W R/W
SaX_EN[1] SaX_EN[2] SaX_EN[3] SaX_EN[4] SaX[1] SaX[2] SaX[3] SaX[4]
0 0 0 0 1 1 1 1
When the E1/T1B bit of the Global Configuration register is a logic 0, this register is held reset. SaX[1:4]: The code word SaX[1:4], (where X = 4, 5, 6, 7 or 8 as selected by the SaSEL[2:0] bits in the E1 TRAN National Bits Codeword Select register) appears in bit X (where X= 4, 5, 6, 7 or 8 as selected by the SaSEL[2:0] bits) of TS0 in frames 1, 3, 5 and 7 respectively (SMF I), or in frames 9, 11, 13 and 15 respectively (SMF II) of a G.704 CRC-4 multiframe. If X = 4, Sa4[1:4] bits appear in bit 4 of frames 1, 3, 5, and 7 respectively (SMF I) or in bit 4 of frames 9, 11, 13, and 15 (SMF II) of a G.704 CRC-4 multiframe. If X = 8, the codeword is inserted into bit 8 of TS 0 in frames 1, 3, 5 and 7 respectively (SMF I), or in frames 9, 11, 13 and 15 respectively (SMF II) of a G.704 CRC-4 multiframe. The code word written in bits SaX[1:4] is latched internally and is updated every submultiframe. Therefore, if the code word is written into register 7 during SMF I of a G.704 CRC-4 multiframe, it will appear in the SaX[1:4] bits of SMF II of the same multiframe. If the code word is written into register 7 during SMF II of a multiframe, its contents will be latched internally and will appear in SMF I of the next multiframe. Hence, a code written in SMF I of a multiframe is latched internally and appears in bit positions 4, 5, 6, 7, or 8 of TS0 in frames 9, 11, 13, and 15 of the CRC-4 multiframe. Also, a code word written during SMF II of a G.704 CRC-4 multiframe will appear in bit positions 4, 5, 6, 7, or 8 of TS0 in frames 1, 3, 5 and 7 of the subsequent CRC-4 multiframe.
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Note that when Sa8[1:4] has been selected by the SaSEL[2:0] bits, the SaX[1:4] bits are mapped in this register in the reverse order as the SaX[1:4] bits, where X = 4, 5, 6 or 7. That is, Sa8[1] is mapped to bit 0 of this register, Sa8[2] is mapped to bit 1, Sa8[3] is mapped to bit 2, and Sa8[4] is mapped to bit 3. SaX_EN[1:4] Bits SaX_EN[1:4] enable the insertion of codeword bits SaX[1:4] (where X = 4, 5, 6, 7, or 8) respectively. If bits SaX_EN[1: 4] are set to logic 1, then the contents of bits SaX[1:4] are substituted into bit X of TS0 ( where X = 4, 5, 6, 7, or 8) of NFAS frames 1, 3, 5, and 7 of SMF I, or into NFAS frames 9, 11, 13, and 15 of SMF II. If any one or more of the SaX_EN[1:4] bits are set to logic 0, the respective SaX[1:4] register bit is disabled and will not be written into the G.704 CRC multiframe (i.e. the SaX bit that has been disabled will pass through transparently). The SaX_EN bits are valid only when the INDIS bit in the E1-TRAN Configuration register is set to logic 0.
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Register 090H: E1 FRMR Frame Alignment Options Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
R/W R/W R/W R/W R/W R/W R/W
CRCEN CASDIS C2NCIWCK Unused Reserved REFR REFCRCEN REFRDIS
1 0 0 X 0 0 1 0
When the E1/T1B bit of the Global Configuration register is a logic 0 or the UNF bit of the Receive Options register is a logic 1, this register is held reset. This register selects the various framing formats and framing algorithms supported by the FRMR block. CRCEN: The CRCEN bit enables the FRMR to frame to the CRC multiframe. When the CRCEN bit is logic 1, the FRMR searches for CRC multiframe alignment and monitors for errors in the alignment. A logic 0 in the CRCEN bit position disables searching for multiframe and suppresses the OOCMF, CRCE, CMFER, FEBE, CFEBE, RAICCRC, C2NCIW and ICMFPI FRMR status/interrupt bits, forcing them to logic 0. CASDIS: The CASDIS bit enables the FRMR to frame to the Channel Associated Signaling multiframe when set to a logic 0. When CAS is enabled, the FRMR searches for signaling multiframe alignment and monitors for errors in the alignment. A logic 1 in the CASDIS bit position disables searching for multiframe and suppresses the OOSMF and the SMFER FRMR outputs, forcing them to logic 0. C2NCIWCK: The C2NCIWCK bit enables the continuous checking for CRC multiframe in the CRC to non-CRC interworking mode of the E1 FRMR. If this bit is a logic 0, the E1-FRMR will cease searching for CRC multiframe alignment in CRC to non-CRC interworking mode. If this bit is a logic 1, the E1-FRMR will
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continue searching for CRC multiframe alignment, even if CRC to non-CRC interworking has been declared. Reserved: The Reserved bit must be programmed to logic 0 for normal operation. REFR: A transition from logic 0 to logic 1 in the REFR bit position forces the resynchronization to a new frame alignment. The bit must be cleared to logic 0, then set to logic 1 again to generate subsequent re-synchronizations. REFCRCEN: The REFCRCEN bit enables excessive CRC errors ( 915 errors in one second) to force a re-synchronization to a new frame alignment. Setting the REFCRCEN bit position to logic 1 enables reframe due to excessive CRC errors; setting the REFCRCEN bit to logic 0 disables CRC errors from causing a reframe. REFRDIS: The REFRDIS bit disables reframing under any error condition once frame alignment has been found; reframing can be initiated by software via the REFR bit. A logic 1 in the REFRDIS bit position causes the FRMR to remain "locked in frame" once initial frame alignment has been found. A logic 0 allows reframing to occur based on the various error criteria (FER, excessive CRC errors, etc.). Note that while the FRMR remains locked in frame due to REFRDIS=1, a received AIS will not be detected since the FRMR must be out-of-frame to detect AIS.
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Register 091H: E1 FRMR Maintenance Mode Options Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W R R/W R/W R/W R/W
Unused BIT2C SMFASC TS16C RAIC Unused AISC EXCRCERR
X 1 0 0 0 X 0 X
When the E1/T1B bit of the Global Configuration register is a logic 0 or the UNF bit of the Receive Options register is a logic 1, this register is held reset. BIT2C: The BIT2C bit enables the additional criterion that loss of frame is declared when bit 2 in time slot 0 of NFAS frames has been received in error on 3 consecutive occasions: a logic 1 in the BIT2C position enables declaration of loss of frame alignment when bit 2 is received in error; a logic 0 in BIT2C enables declaration of loss of frame alignment based on the absence of FAS frames only. SMFASC: The SMFASC bit selects the criterion used to declare loss of signaling multiframe alignment signal: a logic 0 in the SMFASC bit position enables declaration of loss of signaling multiframe alignment when 2 consecutive multiframe alignment patterns have been received in error; a logic 1 in the SMFASC bit position enables declaration of loss of signaling multiframe when 2 consecutive multiframe alignment patterns have been received in error or when time slot 16 contains logic 0 in all bit positions for 1 or 2 multiframes based on the criterion selected by TS16C. TS16C: The TS16C bit selects the criterion used to declare loss of signaling multiframe alignment signal when enabled by the SMFASC: a logic 0 in the TS16C bit position enables declaration of loss of signaling multiframe alignment when time slot 16 contains logic 0 in all bit positions for 1 multiframe; a logic 1 in the TS16C bit position enables declaration of loss of
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signaling multiframe when time slot 16 contains logic 0 in all bit positions for 2 consecutive signaling multiframes. RAIC: The RAIC bit selects the criterion used to declare a Remote Alarm Indication (RAI). If RAIC is logic 0, the RAIV indication is asserted upon reception of any A=1 (bit 3 of NFAS frames) and is deasserted upon reception of any A=0. If RAIC is logic 1, the RAIV indication is asserted if A=1 is received on 4 or more consecutive occasions, and is cleared upon reception of any A=0. AISC : The AISC bit selects the criterion used for determining AIS alarm indication. If AISC is logic 0, AIS is declared if there is a loss of frame (LOF) indication and a 512-bit period is received with less than 3 zeros. If AISC is a logic 1, AIS is declared if less than 3 zeros are detected in each of 2 consecutive 512-bit periods and is cleared when 3 or more zeros are detected in each of 2 consecutive 512-bit intervals. EXCRCERR: The EXCRCERR bit is an active high status bit indicating that excessive CRC evaluation errors (i.e., 915 errors in one second) have occurred, thereby initiating a reframe if enabled by the REFCRCNE bit of the E1 FRMR Frame Alignment Options register. The EXCRCERR bit is reset to logic 0 after the register is read.
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Register 092H: E1 FRMR Framing Status Interrupt Enable Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
R/W R/W R/W R/W R/W R/W R/W R/W
C2NCIWE OOFE OOSMFE OOCMFE COFAE FERE SMFERE CMFERE
0 0 0 0 0 0 0 0
When the E1/T1B bit of the Global Configuration register is a logic 0 or the UNF bit of the Receive Options register is a logic 1, this register is held reset. C2NCIWE, OOFE, OOSMFE and OOCMFE: A logic one in bits C2NCIWE, OOFE, OOSMFE and OOCMFE enables the generation of an interrupt on a change of state of C2NCIWV, OOFV, OOSMFV and OOCMFV bits respectively of the E1 FRMR Framing Status register. COFAE: A logic one in the COFAE bit enables the generation of an interrupt when the position of the frame alignment has changed. FERE: A logic one in the FERE bit enables the generation of an interrupt when an error has been detected in the frame alignment signal. SMFERE: A logic one in the SMFERE bit enables the generation of an interrupt when an error has been detected in the signaling multiframe alignment signal. CMFERE: A logic one in the CMFERE bit enables the generation of an interrupt when an error has been detected in the CRC multiframe alignment signal.
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Register 093H: E1 FRMR Maintenance/Alarm Status Interrupt Enable Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
R/W R/W R/W R/W R/W R/W R/W R/W
RAIE RMAIE AISDE Reserved REDE AISE FEBEE CRCEE
0 0 0 0 0 0 0 0
When the E1/T1B bit of the Global Configuration register is a logic 0 or the UNF bit of the Receive Options register is a logic 1, this register is held reset. RAIE, RMAIE, AISDE, REDE and AISE: A logic one in bits RAIE, RMAIE, AISDE, REDE or AISE enables the generation of an interrupt on a change of state of the RAIV, RMAIV, AISD, RED and AIS bits respectively of the E1 FRMR Maintenance/Alarm Status register. Reserved: This bit must be set to a logic 0 for correct operation. FEBEE: When the FEBEE bit is a logic one, an interrupt is generated when a logic zero is received in the Si bits of frames 13 or 15. CRCEE: When the CRCEE bit is a logic one, an interrupt is generated when calculated CRC differs from the received CRC remainder.
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Register 094H: E1 FRMR Framing Status Interrupt Indication Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
R R R R R R R R
C2NCIWI OOFI OOSMFI OOCMFI COFAI FERI SMFERI CMFERI
X X X X X X X X
When the E1/T1B bit of the Global Configuration register is a logic 0 or the UNF bit of the Receive Options register is a logic 1, this register is held reset. A logic 1 in any bit position of this register indicates which framing status generated an interrupt by changing state. C2NCIWI, OOFI, OOSMFI, OOCMFI, and COFAI: C2NCIWI, OOFI, OOSMFI, OOCMFI, and COFAI indicate when the corresponding status has changed state from logic 0 to logic 1 or vice-versa. FERI, SMFERI, CMFERI: FERI, SMFERI, CMFERI indicate when a framing error, signaling multiframe error or CRC multiframe error event has been detected; these bits will be set if one or more errors have occurred since the last register read. The interrupt indications within this register work independently from the interrupt enable bits, allowing the microprocessor to poll the register to determine the state of the framer. The contents of this register are cleared to logic 0 after the register is read; the interrupt is also cleared if it was generated by any of the Framing Status outputs.
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Register 095H: E1 FRMR Maintenance/Alarm Status Interrupt Indication Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
R R R R R R R
RAII RMAII AISDI Unused REDI AISI FEBEI CRCEI
X X X X X X X X
When the E1/T1B bit of the Global Configuration register is a logic 0 or the UNF bit of the Receive Options register is a logic 1, this register is held reset. A logic 1 in any bit position of this register indicates which maintenance or alarm status generated an interrupt by changing state. RAII, RMAII, AISDI, REDI, and AISI: RAII, RMAII, AISDI, REDI, and AISI indicate when the corresponding FRMR Maintenance/Alarm Status register bit has changed state from logic 0 to logic 1 or vice-versa. FEBEI: The FEBEI bit becomes a logic one when a logic zero is received in the Si bits of frames 13 or 15. CRCEI: The CRCEI bit becomes a logic one when a calculated CRC differs from the received CRC remainder. The bits in this register are set by a single error event. The interrupt indications within this register work independently from the interrupt enable bits, allowing the microprocessor to poll the register to determine the state of the framer. The contents of this register are cleared to logic 0 after the register is read; the interrupt is also cleared if it was generated by one of the Maintenance/Alarm Status events.
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Register 096H: E1 FRMR Framing Status Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
R R R R R R R R
C2NCIWV OOFV OOSMFV OOCMFV OOOFV RAICCRCV CFEBEV V52LINKV
X X X X X X X X
When the E1/T1B bit of the Global Configuration register is a logic 0 or the UNF bit of the Receive Options register is a logic 1, this register is held reset. Reading this register returns the current state value of the C2NCIW, OOF, OOSMF, OOCMF, OOOF and RAICCRC FRMR framing statuses. C2NCIWV: The C2NCIWV bit is set to logic one while the FRMR is operating in CRC to non-CRC interworking mode. The C2NCIWV bit goes to a logic zero once when the FRMR exits CRC to non-CRC interworking mode. OOFV: The OOFV bit is a logic one when basic frame alignment has been lost. The OOFV bit goes to a logic zero once frame alignment has been regained. OOSMFV: The OOSMFV bit is a logic one when the signaling multiframe alignment has been lost. The OOSMFV bit becomes a logic zero once signaling multiframe has been regained. OOCMFV: The OOCMFV bit is a logic one when the CRC multiframe alignment has been lost. The OOCMFV bit becomes a logic zero once CRC multiframe has been regained.
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OOOFV: This bit indicates the current state of the out of offline frame (OOOF) indicator. OOOFV is asserted when the offline framer in the CRC multiframe find procedure is searching for frame alignment. RAICCRCV: This bit indicates the current state of the RAI and continuous CRC (RAICCRC) indicator. RAICCRCV is asserted when the remote alarm (A bit) is set high and the CRC error (E bit) is set low for a period of 10 ms. CFEBEV: This bit indicates the current state of the continuous FEBE (CFEBE) indicator. CFEBEV is asserted when the CRC error (E bit) is set high on more than 990 occasions in each second (out of 1000 possible occasions) for the last 5 consecutive seconds. V52LINKV: This bit indicates the current state of the V5.2 link (V52LINK) identification signal indicator. V52LINKV is asserted if 2 out of the last 3 received Sa7 bits are a logic 0.
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Register 097H: E1 FRMR Maintenance/Alarm Status Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
R R R R R
RAIV RMAIV AISD Unused RED AIS Unused Unused
X X X X X X X X
When the E1/T1B bit of the Global Configuration register is a logic 0 or the UNF bit of the Receive Options register is a logic 1, this register is held reset. Reading this register returns the current state value of the RAI, RMAI, AISD, RED, and AIS maintenance/alarm statuses. RAIV: The RAIV bit indicates the remote alarm indication (RAI) value. The RAIV bit is set to logic one when the "A" bit (bit 3 in time slot 0 of the non-frame alignment signal frame) has been logic one for an interval specified by the RAIC bit in the E1 FRMR Maintenance Mode Options register. When RACI is logic 1, RAIV is set when A=1 for 4 or more consecutive intervals, and is cleared upon reception of any A=0. When RACI is logic 0, RAI is set upon reception of any A=1, and is cleared upon reception of any A=0. The RAIV output is updated every two frames. RMAIV: The RMAIV bit indicates the remote multiframe alarm indication (RMAI) value. The RMAIV bit is set to logic one when the "Y" bit (bit 6 in time slot 16 in frame 0 of the signaling multiframes) has been a logic one for 3 consecutive signaling multiframes, and is cleared upon reception of any Y=0. The RMAIV bit is updated every 16 frames. AISD: The AISD bit indicates the alarm indication signal (AIS) detect value. The AISD bit is set to logic one when the incoming data stream has a low zero-bit density for an interval specified by the AISC bit in the E1 FRMR Maintenance
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Mode Options register. When AISC is logic 0, AISD is asserted when 512-bit periods have been received with 2 or fewer zeros. The indication is cleared when a 512-bit period is received with 3 or more zeros. When AISC is logic 1, AISD is asserted when two consecutive 512 bit periods have been received with 2 or fewer zeros. The indication is cleared when 2 consecutive 512-bit periods are received, with each period containing 3 or more zeros. The AISD bit is updated once every 512-bit period. RED: The RED bit is a logic one if an out of frame condition has persisted for 100 ms. The RED bit returns to a logic zero when a out of frame condition has been absent for 100 ms. AIS: The AIS bit is a logic one when an out of frame all-ones condition has persisted for 100 ms. The AIS bit returns to a logic zero when the AIS condition has been absent for 100 ms.
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Register 098H: E1 FRMR Timeslot 0 International/National Bits Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
R R R R R R R R
Si[1] Si[0] A Sa[4] Sa[5] Sa[6] Sa[7] Sa[8]
X X X X X X X X
When the E1/T1B bit of the Global Configuration register is a logic 0 or the UNF bit of the Receive Options register is a logic 1, this register is held reset. This register returns the International and National bits from TS0 of incoming frames. The Si[1:0], A and Sa[4:8] bits map to TS0 frames as shown in Table 62.
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Table 62
- Timeslot 0 Bit Position Allocation
Frame FAS NFAS Si [1]:
1 Si[1] Si[0]
2 0 1
3 0 A
4 1 Sa[4]
5 1 Sa[5]
6 0 Sa[6]
7 1 Sa[7]
8 1 Sa[8]
Reading the Si[1] bit returns the International bit in the last received FAS frame. This bit is updated upon generation of the IFPI interrupt on FAS frames. Si[0]: Reading the Si[0] bit returns the International bit in the last received NFAS frame. This bit is updated upon generation of the IFPI interrupt on NFAS frames. A: Reading the A bit position returns the Remote Alarm Indication (RAI) bit in the last received NFAS frame. This bit is updated upon generation of the IFPI interrupt on NFAS frames. Sa[4:8]: Reading these bits returns the National bit values in the last received NFAS frame. This bit is updated upon generation of the IFPI interrupt on NFAS frames.
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Register 099H: E1 FRMR CRC Error Counter - LSB Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
R R R R R R R R
CRCERR[7] CRCERR[6] CRCERR [5] CRCERR [4] CRCERR [3] CRCERR [2] CRCERR [1] CRCERR [0]
X X X X X X X X
When the E1/T1B bit of the Global Configuration register is a logic 0 or the UNF bit of the Receive Options register is a logic 1, this register is held reset. CRCERR[7:0]: The CRCERR[7:0] register bits contain the least significant byte of the 10-bit CRC error counter value, which is updated every second.
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Register 09AH: E1 FRMR CRC Error Counter - MSB/Timeslot 16 Extra Bits Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
R R R R R R R R
OVR NEWDATA X[3] Y X[1] X[0] CRCERR [9] CRCERR [8]
0 0 X X X X X X
When the E1/T1B bit of the Global Configuration register is a logic 0 or the UNF bit of the Receive Options register is a logic 1, this register is held reset. This register contains the most significant two bits of the 10-bit CRC error counter value, updated every second. NEWDATA: The NEWDATA flag bit indicates that the CRCERR counter register contents have been updated with a new count value accumulated over the last 1 second interval. It is set to logic 1 when the CRC error counter data is transferred into the counter registers, and is reset to logic 0 when this register is read. This bit can be polled to determine the 1 second timing boundary used by the FRMR. OVR: The OVR flag bit indicates that the CRCERR counter register contents have not been read within the last 1 second interval, and therefore have been overwritten. It is set to logic 1 if CRC error counter data is transferred into the counter registers before the previous data has been read out, and is reset to logic 0 when this register is read. X[3], Y, X[1], X[0]: Reading these bits returns the value of the Extra bits (X[3] and X1:0]) and the Remote Signaling Multiframe Alarm bit (Y) in Frame 0, Timeslot 16 of the last received signaling multiframe. These bits are updated upon generation of the IFPI interrupt on NFAS frames. They map to timeslot 16 as shown in Table
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63. Note that the contents of this register are not updated while the E1FRMR is out of frame.
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Table 63
- Signaling Multiframe Timeslot 16, Frame 0 Bit Positions
Bit
1 0
2 0
3 0
4 0
5 X[3]
6 Y
7 X[1]
8 X[0]
CRCERR[9:8]: The CRCERR[9:8] register bits contain the two most significant bits of the 10bit CRC error counter value, which is updated every second. This CRC error count is distinct from that of PMON because it is guaranteed to be an accurate count of the number of CRC errors in one second; whereas, PMON relies on externally initiated transfers which may not be one second apart.
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Register 09BH: E1 FRMR National Bit Codeword Interrupt Enables Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
R/W R/W R/W R/W R/W R/W R/W R/W
SaSEL[2] SaSEL[1] SaSEL[0] Sa4E Sa5E Sa6E Sa7E Sa8E
0 0 0 0 0 0 0 0
When the E1/T1B bit of the Global Configuration register is a logic 0 or the UNF bit of the Receive Options register is a logic 1, this register is held reset. SaSEL[2:0]: The SaSEL[2:0] bits selects which National Bit Codeword appears in the SaX[1:4] bits of the National Bit Codeword register. These bits map to the codeword selection as shown in Table 64:
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Table 64
- E1 FRMR Codeword Select
SaSEL[2:0] 001 010 011 100 101 110 111 000
National Bit Codeword Undefined Undefined Undefined Sa4 Sa5 Sa6 Sa7 Sa8
Sa4E, Sa5E, Sa6E, Sa7E, Sa8E: The National Use interrupt enables allow changes in Sa code word values to generate an interrupt. If SaXE is a logic 1, a logic 1 in the corresponding SaXI bit of the E1 FRMR National Bit Codeword Interrupts register will result in the assertion low of the INTB output. The interrupt enable should be logic 0 for any bit receiving a HDLC datalink.
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Register 09CH: E1 FRMR National Bit Codeword Interrupts Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R R R R R
Unused Unused Unused Sa4I Sa5I Sa6I Sa7I Sa8I
X X X X X X X X
When the E1/T1B bit of the Global Configuration register is a logic 0 or the UNF bit of the Receive Options register is a logic 1, this register is held reset. Sa4I, Sa5I, Sa6I, Sa7I, Sa8I: The National Use interrupt status bits indicate if the debounced version of the individual bits has changed since the last time this register has been read. A logic 1 in one of the bit positions indicates a new nibble codeword is available in the associated SaX[1:4] bits in the National Bit Codeword registers, where N is 4 through 8. If the associated SaXE bit in the E1 FRMR National Bit Interrupt Enables register is a logic 1, a logic 1 in the SaXI results in the assertion of the INTB output.
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Register 09DH: E1 FRMR National Bit Codeword Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R R R R
Unused Unused Unused Unused SaX[1] SaX[2] SaX[3] SaX[4]
X X X X X X X X
When the E1/T1B bit of the Global Configuration register is a logic 0 or the UNF bit of the Receive Options register is a logic 1, this register is held reset. SaX[1:4]: Reading these bits returns the SaX nibble code word extracted from the submultiframe, where `X' corresponds to the National bit selected by the SaSEL[2:0] bits in the E1 FRMR National Bit Codeword Interrupt Enables register. SaX[1] is from the first SaX bit of the submultiframe; SaX[4] is from the last. A change in the codeword values sets the SaI[X] bit of the E1 FRMR National Bits Codeword Interrupts register.
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Register 09EH: E1 FRMR Frame Pulse/Alarm/V5.2 Link ID Interrupt Enables Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
R/W R/W R/W R/W R/W R/W R/W R/W
OOOFE RAICCRCE CFEBEE V52LINKE IFPE ICSMFPE ICMFPE ISMFPE
0 0 0 0 0 0 0 0
When the E1/T1B bit of the Global Configuration register is a logic 0 or the UNF bit of the Receive Options register is a logic 1, this register is held reset. OOOFE: A logic one in the OOOFE bit enables the generation of an interrupt when the out of offline frame interrupt (OOOFI) is asserted. RAICCRCE: A logic one in the RAICCRCE bit enables the generation of an interrupt when a RAI and Continuous CRC condition has been detected in the incoming data stream. CFEBEE: A logic one in the CFEBEE bit enables the generation of an interrupt when continuous FEBEs have been detected in the incoming data stream. V52LINKE: A logic one in the V52LINKE bit enables the generation of an interrupt when a V5.2 link identification has been detected in the Sa7 bits. IFPE: The input frame pulse interrupt enable bit allows interrupts to be generated on each basic frame pulse. If IFPE is a logic 1, a logic 1 in the IFPI bit of the Frame Pulse Interrupts register will result in the assertion low of the INTB output.
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ICSMFPE: The input frame pulse interrupt enable bit allows interrupts to be generated on each CRC submultiframe pulse. If ICSMFPE is a logic 1, a logic 1 in the ICSMFPI bit of the Frame Pulse Interrupts register will result in the assertion low of the INTB output. ICMFPE: The input frame pulse interrupt enable bit allows interrupts to be generated on each CRC multiframe pulse. If ISMFPE is a logic 1, a logic 1 in the ISMFPI bit of the Frame Pulse Interrupts register will result in the assertion low of the INTB output. ISMFPE: The input frame pulse interrupt enable bit allows interrupts to be generated on each signalling multiframe pulse. If ISMFPE is a logic 1, a logic 1 in the ISMFPI bit of the Frame Pulse Interrupts register will result in the assertion low of the INTB output.
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Register 09FH: E1 FRMR Frame Pulse/Alarm Interrupts Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
R R R R R R R R
OOOFI RAICCRCI CFEBEI V52LINKI IFPI ICSMFPI ICMFPI ISMFPI
X X X X X X X X
When the E1/T1B bit of the Global Configuration register is a logic 0 or the UNF bit of the Receive Options register is a logic 1, this register is held reset. OOOFI: The OOOFI bit indicates when the out of offline frame indicator (OOOFV) changes state. RAICCRCI: The RAICCRCI bit indicates when a RAI and Continuous CRC condition has been detected in the incoming data stream. This interrupt is triggered when the remote alarm (A bit) is set high and the CRC error (E bit) is set low for a period of 10 ms. CFEBEI: The CFEBEI bit indicates when continuous FEBEs have been detected in the incoming data stream. This interrupt is triggered when the CRC error (E bit) is set high on more than 990 occasions in each second (out of 1000 possible occasions) for 5 consecutive seconds. V52LINKI: V52LINKI indicates when a V5.2 link identification signal has been detected or lost in the Sa7 bits. This bit will toggle any time the V52LINKV bit changes state.
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IFPI: The input frame pulse interrupt status bit is asserted at timeslot 1, bit position 1 of the frame in the incoming data stream. ICSMFPI: The input CRC submultiframe alignment frame pulse interrupt status bit is asserted at timeslot 1, bit position 1 of frame 0 of the CRC submultiframe in the incoming data stream. ICMFPI: The input CRC multiframe alignment frame pulse interrupt status bit is asserted at timeslot 1, bit position 1 of frame 0 of the CRC multiframe in the incoming data stream. ISMFPI: The input signaling multiframe alignment frame pulse interrupt status bit is asserted at timeslot 17, bit position 1 of frame 0 of the signaling multiframe in the incoming data stream.
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Register 0A8H (#1), 0B0H (#2), 0B8H (#3): TDPR Configuration Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 EN:
R/W R/W R/W R/W R/W R/W R/W
FLGSHARE FIFOCLR PREN Unused EOM ABT CRC EN
1 0 0 X 0 0 1 0
The EN bit enables the TDPR functions. When EN is set to logic 1, the TDPR is enabled and flag sequences are sent until data is written into the TDPR Transmit Data register. When the EN bit is set to logic 0, the TDPR is disabled and overwrites the incoming backplane data with an all 1's pattern. CRC: The CRC enable bit controls the generation of the CCITT_CRC frame check sequence (FCS). Setting the CRC bit to logic 1 enables the CCITT-CRC generator and appends the 16-bit FCS to the end of each message. When the CRC bit is set to logic 0, the FCS is not appended to the end of the message. The CRC type used is the CCITT-CRC with generator polynomial x16 + x12 + x5 + 1. The high order bit of the FCS word is transmitted first. . CRC FCS is also appended to the performance report data transmitted from the T1-APRM if CRC is set to logic 1. ABT: The Abort (ABT) bit controls the sending of the 7 consecutive ones HDLC abort code. Setting the ABT bit to a logic 1 causes the 11111110 code (the 0 is transmitted first) to be transmitted after the last byte from the TDPR FIFO is transmitted. The FIFO is then reset. All data in the FIFO will be lost. Aborts are continuously sent and the FIFO is held in reset until this bit is reset to a logic 0. At least one Abort sequence will be sent when the ABT bit transitions from logic 0 to logic 1. Note that T1-APRM performance report insertion takes precedence over the ABT register bit. When a performance report frame is available, the TDPR will transmit 2 flag sequences before, and 1 or 2 flag
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sequences (depending on the FLGSHARE bit setting) after the performance report frame. If the ABT bit is still set, the TDPR will then transmit the Abort sequence again. EOM: The EOM bit indicates that the last byte of data written in the Transmit Data register is the end of the present data packet. If the CRC bit is set then the 16-bit FCS word is appended to the last data byte transmitted and a continuous stream of flags is generated. The EOM bit is cleared upon a write to the TDPR Transmit Data register. PREN: The PREN bit enables performance reports from the T1-APRM to be transmitted. When PREN is a logic 1, the message arbitrator circuit will insert the T1-APRM performance report as soon as it is finished any packet whose transmission is already in progress and the delimiting flags. When PREN is a logic 0, the message arbitrator circuit will ignore requests from the T1-APRM. This bit has no effect for TDPR #2 and TDPR #3. FIFOCLR: The FIFOCLR bit resets the TDPR FIFO. When set to logic 1, FIFOCLR will cause the TDPR FIFO to be cleared. There is a maximum delay of one T1 or E1 clock cycle between the setting of this register bit and the execution of the FIFO clear operation. FLGSHARE: The FLGSHARE bit configures the TDPR to share the opening and closing flags between successive frames. If FLGSHARE is logic 1, the opening and closing flags between successive frames are shared. If FLGSHARE is logic 0, separate closing and opening flags are inserted between successive frames.
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Register 0A9H (#1), 0B1H (#2), 0B9H (#3): TDPR Upper Transmit Threshold Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 UTHR[6:0]: R/W R/W R/W R/W R/W R/W R/W
Unused UTHR[6] UTHR[5] UTHR[4] UTHR[3] UTHR[2] UTHR[1] UTHR[0]
X 1 0 0 0 0 0 0
The UTHR[6:0] bits define the TDPR FIFO fill level which will automatically cause the bytes stored in the TDPR FIFO to be transmitted. Once the fill level exceeds the UTHR[6:0] value, transmission will begin. Transmission will not stop until the last complete packet is transmitted and the TDPR FIFO fill level is below UTHR[6:0] + 1. The value of UTHR[6:0] must always be greater than the value of LINT[6:0] unless both values are equal to 00H.
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Register 0AAH (#1), 0B2H (#2), 0BAH (#3): TDPR Lower Interrupt Threshold Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 LINT[6:0]: R/W R/W R/W R/W R/W R/W R/W
Unused LINT[6] LINT[5] LINT[4] LINT[3] LINT[2] LINT[1] LINT[0]
X 0 0 0 0 1 1 1
The LINT[6:0] bits define the TDPR FIFO fill level which causes an internal interrupt (LFILLI) to be generated. Once the TDPR FIFO level decrements to empty or to a value less than LINT[6:0], LFILLI and BLFILL will be set to logic 1. LFILLI will cause an interrupt on INTB if LFILLE is set to logic 1. The value of LINT[6:0] must always be less than the value of UTHR[6:0] unless both values are equal to 00H.
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Register 0ABH (#1), 0B3H (#2), 0BBH (#3): TDPR Interrupt Enable Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 LFILLE: R/W R/W R/W R/W R/W
Unused Unused Unused PRINTE FULLE OVRE UDRE LFILLE
X X X 0 0 0 0 0
If LFILLE is a logic 1, a transition to logic 1 on LFILLI will generate an interrupt on INTB. UDRE: If UDRE is a logic 1, a transition to logic 1 on UDRI will generate an interrupt on INTB. OVRE: If OVRE is a logic 1, a transition to logic 1 on OVRI will generate an interrupt on INTB. FULLE: If FULLE is a logic 1, a transition to logic 1 on FULLI will generate an interrupt on INTB. PRINTE: If PRINTE is a logic 1, a transition to logic 1 on PRINTI will generate an interrupt on INTB.
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Register 0ACH (#1), 0B4H (#2), 0BCH (#3): TDPR Interrupt Status Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R R R R R R R
Unused FULL BLFILL PRINTI FULLI OVRI UDRI LFILLI
X X X X X X X X
Writing to this register will clear the underrun condition if it has occurred. Consecutive writes to the TDPR Configuration and TDPR Transmit Data register and reads of the TDPR Interrupt Status register should not occur at rates greater than that of TCLKO. LFILLI: The LFILLI bit will transition to logic 1 when the TDPR FIFO level transitions to empty or falls below the value of LINT[6:0] programmed in the TDPR Lower Interrupt Threshold register. LFILLI will assert INTB if it is a logic 1 and LFILLE is programmed to logic 1. LFILLI is cleared when this register is read. UDRI: The UDRI bit will transition to 1 when the TDPR FIFO underruns. That is, the TDPR was in the process of transmitting a packet when it ran out of data to transmit. UDRI will assert INTB if it is a logic 1 and UDRE is programmed to logic 1. UDRI is cleared when this register is read. OVRI: The OVRI bit will transition to 1 when the TDPR FIFO overruns. That is, the TDPR FIFO was already full when another data byte was written to the TDPR Transmit Data register. OVRI will assert INTB if it is a logic 1 and OVRE is programmed to logic 1. OVRI is cleared when this register is read.
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FULLI: The FULLI bit will transition to logic 1 when the TDPR FIFO is full. FULLI will assert INTB if it is a logic 1 and FULLE is programmed to logic 1. FULLI is cleared when this register is read. PRINTI: The PRINTI bit will transition to logic 1 when a performance report is ready to be transmitted from the T1-APRM. PRINTI will assert INTB if it is a logic 1 and PRINTE is programmed to logic 1. PRINTI is cleared when this register is read. BLFILL: The BLFILL bit is set to logic 1 if the current FIFO fill level is below the LINT[7:0] level or is empty. FULL: The FULL bit reflects the current condition of the TDPR FIFO. If FULL is a logic 1, the TDPR FIFO already contains 128-bytes of data and can accept no more.
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Register 0ADH (#1), 0B5H (#2), 0BDH (#3): TDPR Transmit Data Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
R/W R/W R/W R/W R/W R/W R/W R/W
TD[7] TD[6] TD[5] TD[4] TD[3] TD[2] TD[1] TD[0]
X X X X X X X X
Consecutive writes to the TDPR Configuration and TDPR Transmit Data register and reads of the TDPR Interrupt Status register should not occur at rates greater than that of TCLKO TD[7:0]: The TD[7:0] bits contain the data to be transmitted on the data link. Data written to this register is serialized and transmitted (TD[0] is transmitted first).
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Registers 0C0H (#1), 0C8H (#2), 0D0H (#3): RDLC Configuration Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 EN: R/W R/W R/W R/W R/W
Unused Unused Unused Reserved MEN MM TR EN
X X X 0 0 0 0 0
The enable (EN) bit controls the overall operation of the RDLC. When EN is set to logic 1, RDLC is enabled; when set to logic 0, RDLC is disabled. When the RDLC is disabled, the FIFO buffer and interrupts are all cleared. When the RDLC is enabled, it will immediately begin looking for flags. TR: Setting the terminate reception (TR) bit to logic 1 forces the RDLC to immediately terminate the reception of the current data frame, empty the FIFO buffer, clear the interrupts, and begin searching for a new flag sequence. The RDLC handles a terminate reception event in the same manner as it would the toggling of the EN bit from logic 1 to logic 0 and back to logic 1. Thus, the RDLC state machine will begin searching for flags. An interrupt will be generated when the first flag is detected. The TR bit will reset itself to logic 0 after a rising and falling edge have occurred on the CLK input, once the write strobe (CBI[9]) goes high. If the Configuration Register is read after this time, the TR bit value returned will be logic 0. MEN: Setting the Match Enable (MEN) bit to logic 1 enables the detection and storage in the FIFO of only those packets whose first data byte matches either of the bytes written to the Primary or Secondary Match Address Registers, or the universal all ones address. When the MEN bit is logic 0, all packets received are written into the FIFO.
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MM: Setting the Match Mask (MM) bit to logic 1 ignores the PA[1:0] bits of the Primary Address Match Register, the SA[1:0] bits of the Secondary Address Match Register, and the two least significant bits of the universal all ones address when performing the address comparison. Reserved: This bit must be set to logic 0 for correct operation.
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Registers 0C1H (#1), 0C9H (#2), 0D1H (#3): RDLC Interrupt Control Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
R/W R/W R/W R/W R/W R/W R/W R/W
INTE INTC[6] INTC[5] INTC[4] INTC[3] INTC[2] INTC[1] INTC[0]
0 0 0 0 0 0 0 0
The contents of the Interrupt Control Register should only be changed when the EN bit in the Configuration Register is logic 0. This prevents any erroneous interrupt generation. INTC[6:0]: These bits control the assertion of FIFO fill level set point interrupts. A value of 0 in INTC[6:0] is interpreted as decimal 128. INTE: The Interrupt Enable bit (INTE) must be set to logic 1 to allow the internal interrupt status to be propagated to the INTB output.
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Registers 0C2H (#1), 0CAH (#2), 0D2H (#3): RDLC Status Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 INTR:
R R R R R R R R
FE OVR COLS PKIN PBS[2] PBS[1] PBS[0] INTR
X X X X X X X X
The interrupt (INTR) bit is logic 1 if the RDLC has an active interrupt status. An RDLC interrupt is generated 1) when the number of bytes specified by the INTC[6:0] bits of the RDLC Interrupt Control register have been received on the data link and have been written into the FIFO, 2) immediately upon detection of a FIFO buffer overrun, as indicated by the OVR in this register, 3) immediately upon writing the last byte of a packet into the FIFO, 4) immediately upon writing the last byte of an aborted packet, or 5) immediately upon detection of the transition from receiving all ones to flags, as indicated by a "001" code in PBS[2:0]. If INTR is logic 1, follow the procedure described in section 14.3: Using the Internal HDLC Receivers PBS[2:0] The packet byte status (PBS[2:0]) bits indicate the status of the data last read from the FIFO. The bits are encoded as follows:
Table 65 PBS[2:0] - Receive Packet Byte Status Significance
000
Data byte read from the FIFO is not special
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PBS[2:0]
Significance
001
The data byte read from the FIFO is the dummy byte that was written into the FIFO when the first HDLC flag sequence (01111110) was detected. This indicates that the data link became active. The data byte read from the FIFO is the dummy byte that was written into the FIFO when the HDLC abort sequence (01111111) was detected. This indicates that the data link became inactive. Reserved The data byte read from the FIFO is the last byte of a normally terminated packet with no CRC error and the packet received had an integer number of bytes. The data byte read from the FIFO must be discard because there was a non-integer number of bytes in the packet. The data byte read from the FIFO is the last byte of a normally terminated packet with a CRC error. The packet was received in error. The data byte read from the FIFO is the last byte of a normally terminated packet with a CRC error and a non-integer number of bytes. The packet was received in error.
010
011 100
101 110
111
PKIN: The Packet In (PKIN) bit is logic 1 when the last byte of a non-aborted packet is written into the FIFO. The PKIN bit is cleared to logic 0 after the Status Register is read. COLS: The Change of Link Status (COLS) bit is set to logic 1 if the RDLC has detected the HDLC flag sequence (01111110) or HDLC abort sequence (01111111) in the data. This indicates that there has been a change in the data link status. The COLS bit is cleared to logic 0 by reading this register or by clearing the EN bit in the Configuration Register. For each change in link status, a byte is written into the FIFO. If the COLS bit is found to be logic 1 then the FIFO must be read until empty. The status of the data link is determined by the PBS bits associated with the data read from the FIFO. OVR: The overrun (OVR) bit is set to logic 1 when data is written over unread data in the FIFO buffer. This bit is not reset to logic 0 until after the Status
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Register is read. While the OVR bit is logic 1, the RDLC and FIFO buffer are held in the reset state, causing the COLS and PKIN bits to be reset to logic 0. FE: The FIFO buffer empty (FE) bit is set to logic 1 when the last FIFO buffer entry is read. The FE bit goes to logic 0 when the FIFO is loaded with new data.
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Registers 0C3H (#1), 0CBH (#2), 0D3H (#3): RDLC Data Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
R R R R R R R R
RD[7] RD[6] RD[5] RD[4] RD[3] RD[2] RD[1] RD[0]
X X X X X X X X
RD[0] corresponds to the first bit of the serial byte received on the DATA input. This register is actually a 128-byte FIFO buffer. If data is available, the FE bit in the FIFO Input Status Register is logic 0. When an overrun is detected, an interrupt is generated and the FIFO buffer is held cleared until the FIFO Input Status Register is read.
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Registers 0C4H (#1), 0CCH (#2), 0D4H (#3): RDLC Primary Address Match Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
R/W R/W R/W R/W R/W R/W R/W R/W
PA[7] PA[6] PA[5] PA[4] PA[3] PA[2] PA[1] PA[0]
1 1 1 1 1 1 1 1
The first byte received after a flag character is compared against the contents of this register. If a match occurs, the packet data, including the matching first byte, is written into the FIFO. PA[0] corresponds to the first bit of the serial byte received on the DATA input. The MM bit in the Configuration Register is used mask off PA[1:0] during the address comparison.
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Registers 0C5H (#1), 0CDH (#2), 0D5H (#3): RDLC Secondary Address Match Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
R/W R/W R/W R/W R/W R/W R/W R/W
SA[7] SA[6] SA[5] SA[4] SA[3] SA[2] SA[1] SA[0]
1 1 1 1 1 1 1 1
The first byte received after a flag character is compared against the contents of this register. If a match occurs, the packet data, including the matching first byte, is written into the FIFO. SA[0] corresponds to the first bit of the serial byte received on the DATA input. The MM bit in the Configuration Register is used mask off SA[1:0] during the address comparison.
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Register 0D6H: CSU Configuration Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 MODE[2:0]:
R/W R/W
CSU_RESET IDDQ_EN Unused Unused
0 0 X X X 0 0 0
R R/W R/W R/W
CSU_LOCK MODE[2] MODE[1] MODE[0]
The MODE[2:0] selects the mode of the CSU. Table 66 indicates the required XCLK frequency, and output frequencies for each mode. Table 66 - Clock Synthesis Mode
XCLK frequency TCLKO frequency
MODE[2:0]
000 001 01X 10X 110 111 CSU_LOCK:
2.048 MHz 1.544 MHz Reserved Reserved Reserved 2.048 MHz
2.048 MHz 1.544 MHz Reserved Reserved Reserved 1.544 MHz
The CSU_LOCK bit may indicate whether or not the embedded clock synthesis unit (CSU) has achieved phase and frequency lock to XCLK. CSU_LOCK is a logic 1 if the divided down synthesized clock frequency is within 244 ppm of the XCLK frequency. A persistent logic 0 in this bit position may indicate a mismatch between the actual and expected XCLK frequency or a problem with the analog supplies (TAVS4 and TAVD4).
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IDDQ_EN: The IDDQ enable bit (IDDQ_EN) is used to configure the embedded CSU for IDDQ tests. When IDDQ_EN is a logic 1, or the IDDQEN bit in the Master Test register (00BH) is a logic 1, the digital outputs of the CSU are pulled to ground. When either the IDDQ_EN bit or IDDQEN bit is set to logic 1, the HIGHZ bit in the XLPG Line Driver Configuration register must also be set to logic 1. CSU_RESET: Setting the CSU_RESET bit to logic 1 causes the embedded CSU to be forced to a frequency much lower than normal operation.
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Register 0D8H: RLPS Equalization Indirect Data Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
R/W R/W R/W R/W R/W R/W R/W R/W
EQ_DATA[31] EQ_DATA[30] EQ_DATA[29] EQ_DATA[28] EQ_DATA[27] EQ_DATA[26] EQ_DATA[25] EQ_DATA[24]
0 0 0 0 0 0 0 0
When the RUNI bit of the Receive Line Interface Configuration register is a logic 1, this register is held reset. EQ_DATA[31:24]: This register consists of 2-parts: read-only and write-only. Writing this register affects the most significant byte of the input-data to the equalization RAM. Reading it returns the MSB of the RAM location indexed by register 0FCH.
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Register 0D9H: RLPS Equalization Indirect Data Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
R/W R/W R/W R/W R/W R/W R/W R/W
EQ_DATA[23] EQ_DATA[22] EQ_DATA[21] EQ_DATA[20] EQ_DATA[19] EQ_DATA[18] EQ_DATA[17] EQ_DATA[16]
0 0 0 0 0 0 0 0
When the RUNI bit of the Receive Line Interface Configuration register is a logic 1, this register is held reset. EQ_DATA[23:16]: This register consists of 2-parts: read-only and write-only. Writing this register affects the second most significant byte of the input-data to the equalization RAM. Reading it returns the second MSB of the RAM location indexed by register 0FCH.
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Register 0DAH: RLPS Equalization Indirect Data Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
R/W R/W R/W R/W R/W R/W R/W R/W
EQ_DATA[15] EQ_DATA[14] EQ_DATA[13] EQ_DATA[12] EQ_DATA[11] EQ_DATA[10] EQ_DATA[9] EQ_DATA[8]
0 0 0 0 0 0 0 0
When the RUNI bit of the Receive Line Interface Configuration register is a logic 1, this register is held reset. EQ_DATA[15:8]: This register consists of 2-parts: read-only and write-only. Writing this register affects the second least significant byte of the input-data to the equalization RAM. Reading it returns the corresponding bits of the RAM location indexed by register 0FCH.
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Register 0DBH: RLPS Equalization Indirect Data Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
R/W R/W R/W R/W R/W R/W R/W R/W
EQ_DATA[7] EQ_DATA[6] EQ_DATA[5] EQ_DATA[4] EQ_DATA[3] EQ_DATA[2] EQ_DATA[1] EQ_DATA[0]
0 0 0 0 0 0 0 0
When the RUNI bit of the Receive Line Interface Configuration register is a logic 1, this register is held reset. EQ_DATA[7:0]: This register consists of 2-parts: read-only and write-only. Writing this register affects the least significant byte of the input-data to the equalization RAM. Reading it returns the LSB of the RAM location indexed by register 0FCH.
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Register 0DCH: RLPS Equalizer Voltage Reference Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W R/W R/W R/W R/W R/W
Unused Unused EQ_VREF[5] EQ_VREF[4] EQ_VREF[3] EQ_VREF[2] EQ_VREF[1] EQ_VREF[0]
X X 0 0 0 0 0 0
When the RUNI bit of the Receive Line Interface Configuration register is a logic 1, this register is held reset. EQ_VREF[5:0]: This register sets the voltage reference of the analog receiver's equalizer. For T1 mode, the EQ_VREF[5:0] bits must be programmed to 2CH (`b101100). For E1 mode, the EQ_VREF[5:0] bits must be programmed to 34H (`b110100).
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Register 0E0H: PRGD Control Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PDR[1:0]:
R/W R/W R/W R/W R/W R/W R/W R/W
PDR[1] PDR[0] QRSS PS TINV RINV AUTOSYNC MANSYNC
0 0 0 0 0 0 1 0
The PDR[1:0] bits select the content of the four pattern detector registers to be any one of the pattern receive registers, the error count holding registers, or the bit count holding registers. The selection is shown in the following table:
Table 67 PDR[1:0] - Pattern Detector Register Configurations PDR#1 PDR#2 PDR#3 PDR#4
00, 01
Pattern Receive (LSB) Error Count (LSB) Bit Count (LSB)
Pattern Receive Error Count Bit Count
Pattern Receive Error Count Bit Count
Pattern Receive (MSB) Error Count (MSB) Bit Count (MSB)
10 11
QRSS: The quasi-random signal source (QRSS) bit enables the zero suppression feature required when generating a QRSS sequence. More specifically, a one is forced in the transmit stream when QRSS is a logic 1 and the following 14 bit positions in the transmit bit stream generator are all zeros. When QRSS is a logic 0, the zero suppression feature is disabled. Note that the QRSS bit is also interpreted by the PRGD receiver. Accordingly, the receiver
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will expect appropriately placed zero suppression bits when QRSS is a logic 1. PS: The PS bit selects the pattern type. When PS is a logic 1, a repetitive pattern is generated. When PS is a logic 0, a pseudo-random pattern is generated/detected. The PS bit must be programmed to the desired setting before programming any other PRGD registers, otherwise the transmitted pattern may be corrupted. Any time the setting of the PS bit is changed, the rest of the PRGD registers should be reprogrammed. TINV: The TINV bit controls the logical inversion of the generated pattern. When TINV is a logic 1, the data generated is inverted. RINV: The RINV bit controls the logical inversion of the received stream. When RINV is a logic 1, the received data is inverted before being processed by the pattern detector. AUTOSYNC: The AUTOSYNC bit enables the automatic resynchronization of the pattern detector. The automatic resynchronization is activated when 10 or more bit errors are detected in a fixed 48-bit window. When AUTOSYNC is a logic 1, the auto resync feature is enabled. When AUTOSYNC is a logic 0, the auto sync feature is disabled, and pattern resynchronization is accomplished using the MANSYNC bit. MANSYNC: The MANSYNC bit is used to initiate a manual resynchronization of the pattern detector. A low to high transition on MANSYNC initiates the resynchronization.
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Register 0E1H: PRGD Interrupt Enable/Status Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SYNCE:
R/W R/W R/W R R R R R
SYNCE BEE XFERE SYNCV SYNCI BEI XFERI OVR
0 0 0 X X X X X
The SYNCE bit enables the generation of an interrupt when the pattern detector changes synchronization state. When SYNCE is set to logic 1, the interrupt is enabled. BEE: The BEE bit enables the generation of an interrupt when a bit error is detected in the receive data. Bit errors are not flagged unless the pattern detector is synchronized. Loss of synchronization may result in the generation of a bit error interrupt. When BEE is set to logic 1, the interrupt is enabled. XFERE: The XFERE bit enables the generation of an interrupt when an accumulation interval is completed and new values are stored in the receive pattern registers, the bit counter holding registers, and the error counter holding registers. When XFERE is set to logic 1, the interrupt is enabled. SYNCV: The SYNCV bit indicates the synchronization state of the pattern detector. When SYNCV is a logic 1 the pattern detector is synchronized (the pattern detector has observed at least 48 consecutive error free bit periods). When SYNCV is a logic 0, the pattern detector is out of sync (the pattern detector has detected 10 or more bit errors in a fixed 48-bit window).
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SYNCI: The SYNCI bit indicates that the detector has changed synchronization state since the last time this register was read. If SYNCI is logic 1, the pattern detector has gained or lost synchronization at least once. SYNCI is set to logic 0 when this register is read. BEI: The BEI bit indicates that one or more bit errors have been detected since the last time this register was read. When BEI is set to logic 1, at least one bit error has been detected. BEI is set to logic 0 when this register is read. XFERI: The XFERI bit indicates that a transfer of pattern detector data has occurred. A logic 1 in this bit position indicates that the pattern receive registers, the bit counter holding registers and the error counter holding registers have been updated. This update is initiated by writing to one of the pattern detector register locations, or by writing to the Revision/Chip ID/Global PMON Update register. XFERI is set to logic 0 when this register is read. OVR: The OVR bit is the overrun status of the pattern detector registers. A logic 1 in this bit position indicates that a previous transfer (indicated by XFERI being logic 1) has not been acknowledged before the next accumulation interval has occurred and that the contents of the pattern receive registers, the bit counter holding registers and the error counter holding registers have been overwritten. OVR is set to logic 0 when this register is read.
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318
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Register 0E2H: PRGD Shift Register Length Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PL[4:0]: R/W R/W R/W R/W R/W
Unused Unused Unused PL[4] PL[3] PL[2] PL[1] PL[0]
X X X 0 0 0 0 0
PL[4:0] determine the length of the generated pseudo random or repetitive pattern. The pattern length is equal to the value of PL[4:0] + 1.
PROPRIETARY AND CONFIDENTIAL
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Register 0E3H: PRGD Tap Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PT[4:0]: R/W R/W R/W R/W R/W
Unused Unused Unused PT[4] PT[3] PT[2] PT[1] PT[0]
X X X 0 0 0 0 0
PT[4:0] determine the feedback tap position of the generated pseudo random pattern. The feedback tap position is equal to the value of PT[4:0] + 1. Refer to the Operation section for commonly programmed feedback taps and shift register lengths.
PROPRIETARY AND CONFIDENTIAL
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Register 0E4H: PRGD Error Insertion Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 EVENT: R/W R/W R/W R/W
Unused Unused Unused Unused EVENT EIR[2] EIR[1] EIR[0]
X X X X 0 0 0 0
A low to high transition on the EVENT bit causes a single bit error to be inserted in the generated pattern. This bit must be cleared and set again for a subsequent error to be inserted. EIR[2:0]: The EIR[2:0] bits control the insertion of a programmable bit error rate as indicated in Table 68.
Table 68 - Error Insertion Rates Generated Bit Error Rate
EIR[2:0]
000 001 010 011 100 101 110 111
No errors inserted 10-1 10-2 10-3 10-4 10-5 10-6 10-7
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Register 0E8H: PRGD Pattern Insertion #1 Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
R/W R/W R/W R/W R/W R/W R/W R/W
PI[7] PI[6] PI[5] PI[4] PI[3] PI[2] PI[1] PI[0]
0 0 0 0 0 0 0 0
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Register 0E9H: PRGD Pattern Insertion #2 Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
R/W R/W R/W R/W R/W R/W R/W R/W
PI[15] PI[14] PI[13] PI[12] PI[11] PI[10] PI[9] PI[8]
0 0 0 0 0 0 0 0
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Register 0EAH: PRGD Pattern Insertion #3 Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
R/W R/W R/W R/W R/W R/W R/W R/W
PI[23] PI[22] PI[21] PI[20] PI[19] PI[18] PI[17] PI[16]
0 0 0 0 0 0 0 0
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Register 0EBH: PRGD Pattern Insertion #4 Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PI[31:0]:
R/W R/W R/W R/W R/W R/W R/W R/W
PI[31] PI[30] PI[29] PI[28] PI[27] PI[26] PI[25] PI[24]
0 0 0 0 0 0 0 0
PI[31:0] contain the data that is loaded in the pattern generator each time a new pattern (pseudo random or repetitive) is to be generated. When a pseudo random pattern is to be generated, PI[31:0] should be set to FFFFFFFFH. The data is loaded each time pattern insertion register #4 is written. Pattern insertion registers #1 - #3 should be loaded with the desired data before pattern register #4 is written. When a repetitive pattern is transmitted, PI[31] is transmitted first, followed by the remaining bits in sequence down to PI[0]. Subsequently, PI [pattern_length-1] down to PI[0] will be repetitively transmitted, where pattern_length is the decimal value stored in the PRGD length register.
PROPRIETARY AND CONFIDENTIAL
325
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Register 0ECH: PRGD Pattern Detector #1 Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
R R R R R R R R
PD[7] PD[6] PD[5] PD[4] PD[3] PD[2] PD[1] PD[0]
X X X X X X X X
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Register 0EDH: PRGD Pattern Detector #2 Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
R R R R R R R R
PD[15] PD[14] PD[13] PD[12] PD[11] PD[10] PD[9] PD[8]
X X X X X X X X
PROPRIETARY AND CONFIDENTIAL
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Register 0EEH: PRGD Pattern Detector #3 Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
R R R R R R R R
PD[23] PD[22] PD[21] PD[20] PD[19] PD[18] PD[17] PD[16]
X X X X X X X X
PROPRIETARY AND CONFIDENTIAL
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Register 0EFH: PRGD Pattern Detector #4 Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PD[31:0]:
R R R R R R R R
PD[31] PD[30] PD[29] PD[28] PD[27] PD[26] PD[25] PD[24]
X X X X X X X X
Reading PD[31:0] returns the contents of the pattern detector data register selected by the PDR[1:0] bits in the control register. All three detector data registers are updated during an accumulation interval. When PDR[1:0] is set to 00 or 01, reading PD[31:0] returns the contents of the pattern receive register. The 32 bits received immediately before the last accumulation interval are present on PD[31:0]. PD[0] contains the bit received immediately prior to the last accumulation. When PDR[1:0] is set to 10, reading PD[31:0] returns the contents of the error counter holding register. The value in this register represents the number of bit errors that were accumulated during the last accumulation 32 interval, up to a maximum (saturation) value of 2 -1. Note that bit errors are not accumulated while the pattern detector is out of sync. When PDR[1:0] is set to 11, reading PD[31:0] returns the contents of the bit counter holding register. The value in this register represents the total number of bits that were received during the last accumulation interval, up to 32 a maximum (saturation) value of 2 -1. Note that bits are not counted while the pattern detector is out of synchronization. Writing to any of these registers or the Global PMON Update Register causes them to be updated, and the internal counters reset. The XFERI bit in PRGD Enable/Status register will go high once the update is complete, and an interrupt will be generated if enabled.
PROPRIETARY AND CONFIDENTIAL
329
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Register 0F0H: XLPG Line Driver Configuration Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
R/W
HIGHZ Unused Unused
1 X X 0 0 0 0 0
R/W R/W R/W R/W R/W
SCALE[4] SCALE[3] SCALE[2] SCALE[1] SCALE[0]
When the TUNI bit of the Transmit Line Interface Configuration register is a logic 1, this register is held reset. HIGHZ: The HIGHZ bit controls if the TXTIP and TXRING outputs are to be tri-stated or not. When the HIGHZ bit is set to a logic 0, the outputs are enabled. When the HIGHZ bit is set to a logic 1 then the outputs are put into high impedance. Setting HIGHZ to logic 1 has the same effect as setting SCALE[4:0] to 00H. SCALE[4:0]: The SCALE[4:0] bits control the amplitude of the D/A output waveform. The full scale output amplitude is increased by increments of 11.14 mA. A value of 0 (00H) tristates the output while the maximum value of 21 (15H) sets the full scale current to 234 mA.
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Table 69
- Transmit Output Amplitude SCALE[4:0] Output Amplitude
0 00000 1-20 00001-10100 21 10101 >21 10110-11111
0 mA (tristate) Increments of 11.14 mA for each D/A step 234 mA total Reserved
PROPRIETARY AND CONFIDENTIAL
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Register 0F1H: XLPG Control/Status Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R R/W R/W
Unused Unused Unused Unused Unused OVRFLW Reserved Reserved
X X X X X X 0 1
When the TUNI bit of the Transmit Line Interface Configuration register is a logic 1, this register is held reset. OVRFLW: The overflow detection value bit (OVRFLW) indicates the presence or absence of an overflow condition in the waveform computation pipeline. An overflow occurs when the sum of the five unit interval (UI) samples exceeds the maximum D/A value. The XLPG detects overflows and saturates the output value to minimize their impact on the output signal. Overflows can easily be eliminated by changing the waveform programming. This status bit is set to logic 1 when an overflow condition is detected and it is reset to logic 0 only when this register is read. It is suggested to read this register twice after the programming of a new waveform and transmission of data to ensure the maximum output amplitude is never exceeded. Reserved: The Reserved bits must remain in their default state for correct operation.
PROPRIETARY AND CONFIDENTIAL
332
STANDARD PRODUCT DATA SHEET PMC-1970624 ISSUE 10
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Register 0F2H: XLPG Pulse Waveform Storage Write Address Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
R/W R/W R/W R/W R/W R/W R/W R/W
SAMPLE[4] SAMPLE[3] SAMPLE[2] SAMPLE[1] SAMPLE[0] UI[2] UI[1] UI[0]
0 0 0 0 0 0 0 0
When the TUNI bit of the Transmit Line Interface Configuration register is a logic 1, this register is held reset. UI[2:0]: The pulse waveform write address is composed of a unit interval selector and a sample selector. The unit interval selector (UI[2:0]) selects which unit interval is being written for a given sample. There are 5 unit intervals, numbered from 0 to 4. UI[2:0] can take the values 0H, 1H, 2H, 3H and 4H. The values 5H, 6H and 7H are undefined. SAMPLE[4:0]: The pulse waveform write address is composed of a unit interval selector and a sample selector. The sample selector (SAMPLE[4:0]) selects which sample is being written for a given unit interval. There are 24 samples, numbered from 0 to 23. SAMPLE[4:0] can thus have any value from 00H to 17H. The values from 18H to 1FH are undefined. See the Operation section for more details on setting up waveform templates.
PROPRIETARY AND CONFIDENTIAL
333
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Register 0F3H: XLPG Pulse Waveform Storage Data Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 W W W W W W W
Unused WDAT[6] WDAT[5] WDAT[4] WDAT[3] WDAT[2] WDAT[1] WDAT[0]
X X X X X X X X
When the TUNI bit of the Transmit Line Interface Configuration register is a logic 1, this register is held reset. WDAT[6:0]: This register allows software to program the contents of any one of the 120 internal waveform template registers, addressed by the UI[2:0] and SAMPLE[4:0] bits in the Pulse Waveform Storage Write Address register. When accessing the internal waveform storage registers, the address of the desired register must first be written to the Indirect Address register (the XLPG Pulse Waveform Storage Write Address register). Then, by writing the Indirect Data register (the XLPG Pulse Waveform Storage Data register), the microprocessor can write the data to the selected write address. The value written to the internal pulse waveform storage registers is contained in the signed WDAT[6:0] bits. A signed representation is used (by opposition to a two's complement representation) to make the programming easier. WDAT[6] is the sign bit, WDAT[5] is the most significant data bit and WDAT[0] is the least significant data bit. The data value thus can range from -62 to +63 (-63 is not a valid value due to subsequent conversion into a two's complement representation). See the Operation section for more details on setting up custom waveform templates.
PROPRIETARY AND CONFIDENTIAL
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STANDARD PRODUCT DATA SHEET PMC-1970624 ISSUE 10
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Register 0F4H: XLPG Analog Test Negative Control Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W R/W R/W R/W R/W R/W R/W
Unused TNC[6] TNC[5] TNC[4] TNC[3] TNC[2] TNC[1] TNC[0]
X 0 0 0 0 0 0 0
When the TUNI bit of the Transmit Line Interface Configuration register is a logic 1, this register is held reset. TNC[6:0]: This register controls the nDAC absolute current (both "blowing" the fuses and the software override of the fuses) of the analog transmit line interface unit. TNC[1:5] adjust the offset in steps of 0.78125%, TNC[6] controls the direction (0 is positive, 1 is negative) and TNC[0] is the enable (active low). When TNC[0] is logic 0 and the TRIMF input pin is high, the fuse(s) (as indicated by TNC[1:6]) will be blown. Note that the device must be in analog test mode to enable this control. When TRIMF is low and TNC[0] is logic 0, then TNC[1:6] override the fuses (note this is independent of being in analog test mode).
PROPRIETARY AND CONFIDENTIAL
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Register 0F5H: XLPG Analog Test Positive Control Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W R/W R/W R/W R/W R/W R/W
Unused TPC[6] TPC[5] TPC[4] TPC[3] TPC[2] TPC[1] TPC[0]
X 0 0 0 0 0 0 0
When the TUNI bit of the Transmit Line Interface Configuration register is a logic 1, this register is held reset. TPC[6:0]: This register controls the pDAC absolute current (both "blowing" the fuses and the software override of the fuses) of the analog transmit line interface unit. TPC[1:5] adjust the offset in steps of 0.78125%, TPC[6] controls the direction (0 is positive, 1 is negative) and TPC[0] is the enable (active low). When TPC[0] is logic 0 and the TRIMF input pin is high, the fuse(s) (as indicated by TPC[1:6]) will be blown. Note that the device must be in analog test mode to enable this control. When TRIMF is low and TPC[0] is logic 0, then TPC[1:6] override the fuses (note this is independent of being in analog test mode).
PROPRIETARY AND CONFIDENTIAL
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Register 0F6H: XLPG Fuse Data Select Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W
Unused Unused Unused Unused Unused Unused Unused FDSB
X X X X X X X 0
When the TUNI bit of the Transmit Line Interface Configuration register is a logic 1, this register is held reset. FDSB: This register selects between microprocessor data (FDSB is logic 1) or the value burned into the fuses of the transmit line interface unit (FDSB is logic 0) as the inputs to the XLPG Analog Test Negative Control Register and the XLPG Analog Test Positive Control Register. To write the fuse data into the XLPG Analog Test Negative Control Register and the XLPG Analog Test Positive Control Register, TPC[0] and TNC[0], respectively, must be set to logic 1 and the XLPG Analog Test Negative Control Register and the XLPG Analog Test Positive Control Register must each be written to twice consecutively. (The first write is to activate the outputs of the transmit line interface unit valid, and the second write copies the fuse data into the register.) TPC[0] and TNC[0] should be cleared to lower the likelihood of fuse re-growth.
PROPRIETARY AND CONFIDENTIAL
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Register 0F8H: RLPS Configuration and Status Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
R R R/W R/W R/W R/W R/W
ALOSI ALOSV ALOSE SQUELCHE IDDQ_EN DB_VALID Unused Reserved
X X 0 0 0 X X 1
When the RUNI bit of the Receive Line Interface Configuration register is a logic 1, this register is held reset. Reserved: The Reserved bit must be programmed to logic 1 for correct operation. DB_VALID: The DB_VALID bit indicates if the adaptive equalizer has stabilized. This bit is set if the CABLELOSS signal has not changed by more than 2dB (or +/-8 steps in the RAM table) in more than the count of sampling periods selected by the VALID_PER[1:0] bits of the RLPS Equalizer Configuration register. IDDQ_EN: The IDDQ enable bit (IDDQ_EN) is used to configure the analog receiver for IDDQ tests. When IDDQ_EN is a logic 1, or the IDDQEN bit in the Master Test register (00BH) is a logic 1, the digital outputs of the analog receiver are pulled to ground. SQUELCHE: The output data squelch enable (SQUELCHE) allows control of data squelching in response to an analog LOS of signal condition. When SQUELCHE is set to logic 1, the recovered data are forced to all-zeros if the ALOSV register bit is asserted. When SQUELCHE is set to logic 0, squelching is disabled.
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ALOSE: The loss of signal interrupt enable bit (ALOSE) enables the generation of device level interrupt on a change of Loss of Signal status. When ALOSE is a logic 1, an interrupt is generated by asserting INTB low when there is a change of the ALOSV status. When ALOSE is set to logic 0, interrupts are disabled. ALOSV: The loss of signal value bit (ALOSV) indicates the loss of signal alarm state. This status bit is available for both short haul mode and long haul modes of operation. ALOSI: The loss of signal interrupt bit (ALOSI) is a logic 1 whenever the Loss of Signal indicator state (ALOSV) changes from a logic 0 to a logic 1. This bit is cleared when this register is read.
PROPRIETARY AND CONFIDENTIAL
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Register 0F9H: RLPS ALOS Detection/Clearance Threshold Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W R/W R/W R/W R/W R/W
Unused CLR_THR[2] CLR_THR[1] CLR_THR[0] Unused DET_THR[2] DET_THR[1] DET_THR[0]
X 0 0 0 X 0 0 0
When the RUNI bit of the Receive Line Interface Configuration register is a logic 1, this register is held reset.
Table 70 - ALOS Detection/Clearance Thresholds THR Signal level (dB) Detection/ Clearance Clearance
000 001 010 011 100 101 110 111 DET_THR[2:0]:
9 14.5 20 22 25 30 31 35
Detection and Clearance
Detection and Clearance Detection
DET_THR[2:0] references one of the threshold settings in Table 70 as the ALOS detection criteria. If the incoming signal level is less than or equal to that threshold for N consecutive pulse period, (where N = 16 * the value stored in the RLPS ALOS Detection Period Register) ALOS is declared and interrupt is set. The DET_THR[2:0] bits must be programmed to the same value as the CLR_THR[2:0] bits.
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CLR_THR[2:0]: CLR_THR[2:0] references one of the threshold settings listed in Table 70 as the ALOS clearance criteria. ALOS is cleared when the incoming signal level is greater than or equal to dB below nominal for N consecutive pulse intervals, where N = 16 * CLR_PER stored in the RLPS ALOS Clearance Period Register. The CLR_THR[2:0] bits must be programmed to the same value as the DET_THR[2:0] bits.
PROPRIETARY AND CONFIDENTIAL
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Register 0FAH: RLPS ALOS Detection Period Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
R/W R/W R/W R/W R/W R/W R/W R/W
DET_PER[7] DET_PER[6] DET_PER[5] DET_PER[4] DET_PER[3] DET_PER[2] DET_PER[1] DET_PER[0]
0 0 0 0 0 0 0 1
When the RUNI bit of the Receive Line Interface Configuration register is a logic 1, this register is held reset. DET_PER[7:0]: This register specifies the time duration that the incoming signal level has to remain below the detection threshold in order for the ALOS to be issued. This duration is equal to DET_PER * 16 number of pulse intervals, the resulting range is from 16 to 4080 and thus compliant with all the presently available E1/T1 ALOS detection standards/ recommendations.
PROPRIETARY AND CONFIDENTIAL
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Register 0FBH: RLPS ALOS Clearance Period Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
R/W R/W R/W R/W R/W R/W R/W R/W
CLR_PER[7] CLR_PER[6] CLR_PER[5] CLR_PER[4] CLR_PER[3] CLR_PER[2] CLR_PER[1] CLR_PER[0]
0 0 0 0 0 0 0 1
When the RUNI bit of the Receive Line Interface Configuration register is a logic 1, this register is held reset. CLR_PER[7:0]: This register specifies the time duration that the incoming signal level has to remain above the clearance threshold in order for the ALOS to be cleared. This duration is equal to CLR_PER * 16 number of pulse intervals resulting in a range from 16 to 4080 and thus compliant with all the presently available E1/T1 ALOS clearance standards/ recommendations.
PROPRIETARY AND CONFIDENTIAL
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Register 0FCH: RLPS Equalization Indirect Address Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
R/W R/W R/W R/W R/W R/W R/W R/W
EQ_ADDR[7] EQ_ADDR[6] EQ_ADDR[5] EQ_ADDR[4] EQ_ADDR[3] EQ_ADDR[2] EQ_ADDR[1] EQ_ADDR[0]
0 0 0 0 0 0 0 0
When the RUNI bit of the Receive Line Interface Configuration register is a logic 1, this register is held reset. EQ_ADDR [7:0]: Writing to this register initiates an internal uP access request cycle to the RAM. Depending on the setting of the RWB bit inside register 0FDH, a read or a write will be performed. During a write cycle, the indirect data bits located in registers 0D8H to 0DBH is written into the RAM. For a read request, the content of the addressed RAM location is written into registers 0D8H to 0DBH. This register should be the last register to be written for a uP access. A waiting period of three line rate cycles is needed between the time this register is written to the time the next indirect data bits in registers 0D8H to 0DBH are written.
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PM4351 COMET
COMBINED E1/T1 TRANSCEIVER
Register 0FDH: RLPS Equalization Read/WriteB Select Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
R/W
RWB Unused Unused Unused Unused Unused Unused Unused
1 X X X X X X X
When the RUNI bit of the Receive Line Interface Configuration register is a logic 1, this register is held reset. RWB: This bit selects the operation to be performed on the RAM: when RWB is `1', a read from the equalization RAM is requested; when RWB is set to `0', a write to the RAM is desired.
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PM4351 COMET
COMBINED E1/T1 TRANSCEIVER
Register 0FEH: RLPS Equalizer Loop Status and Control Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
R/W R/W R/W R/W R/W R/W R/W R/W
LOCATION[7] LOCATION[6] LOCATION[5] LOCATION[4] LOCATION[3] LOCATION[2] LOCATION[1] LOCATION[0]
0 0 0 0 0 0 0 0
When the RUNI bit of the Receive Line Interface Configuration register is a logic 1, this register is held reset. LOCATION[7:0]: Writing to this register overwrites a counter which serves as the read address to the equalization RAM. Reading this register returns the current value of the counter
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PM4351 COMET
COMBINED E1/T1 TRANSCEIVER
Register 0FFH: RLPS Equalizer Configuration Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
R/W R/W
VALID_PER[1] VALID_PER[0] Unused Unused
0 0 X X 0 0 1 1
R/W R/W R/W R/W
Reserved EQ_FREQ2] EQ_FREQ[1] EQ_FREQ[0]
When the RUNI bit of the Receive Line Interface Configuration register is a logic 1, this register is held reset. EQ_FREQ[2:0]: The EQ_FREQ[2:0] field selects the frequency of the EQ feedback loop as indicated by Table 71.
Table 71 - Equalization Feedback Frequencies EQ_FREQ[2:0] EQ Feedback Frequency T1 mode E1 mode 24.125 kHz 32.000 kHz 12.063 kHz 16.000 kHz 8.0417 kHz 10.667 kHz 6.0313 kHz 8.0000 kHz 4.8250 kHz 6.40 kHz 4.0208 kHz 5.333 kHz 3.4464 kHz 4.5714 kHz 3.0156 kHz 4.0 kHz
000 001 010 011 100 101 110 111 Reserved:
The Reserved bit must be programmed to logic 1 for correct operation. Note that this bit defaults to logic 0.
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COMBINED E1/T1 TRANSCEIVER
VALID_PER[1:0]: The VALID_PER[1:0] bits select the length of time that the dB loss counter must be stable before DB_VALID is asserted. The duration is measured in number of periods of the EQ feedback loop (specified by the EQ_FREQ bits) as indicated by Table 72.
Table 72 - Valid Period VALID_PER 00 01 10 11 Number of periods 32 64 128 256
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12
TEST FEATURES DESCRIPTION
Simultaneously asserting the CSB, RDB and WRB inputs causes all output pins and the data bus to be held in a high-impedance state. This test feature may be used for board testing. Test mode registers are used to apply test vectors during production testing of the COMET. Test mode registers (as opposed to normal mode registers) are mapped into addresses 100H-1FFH. Test mode registers may also be used for board testing. When all of the constituent Telecom System Blocks within the COMET are placed in test mode 0, device inputs may be read and device outputs may be forced via the microprocessor interface (refer to the section "Test Mode 0" for details).
Notes on Test Mode Register Bits:
1. Writing values into unused register bits has no effect. Reading unused bits can produce either a logic 1 or a logic 0; hence unused register bits should be masked off by software when read. 2. Writeable test mode register bits are not initialized upon reset unless otherwise noted.
PROPRIETARY AND CONFIDENTIAL
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PM4351 COMET
COMBINED E1/T1 TRANSCEIVER
Register 00BH: COMET Master Test Bit Type Function Default
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 W W W W R/W W R/W
Unused IDDQEN PMCATST PMCTST DBCTRL IOTST HIZDATA HIZIO
X X X X 0 0 0 0
This register is used to select COMET test features. All bits, except for PMCTST, PMCATST and IDDQEN, are reset to zero by a hardware reset of the COMET; a software reset of the COMET does not affect the state of the bits in this register. IDDQEN: The IDDQEN bit is used to configure the COMET for IDDQ tests. IDDQEN is cleared when CSB is high and RSTB is low or when IDDQEN is written as logic 0. When the IDDQEN bit is set to logic 1, the HIGHZ bit in the XLPG Line Driver Configuration register must also be set to logic 1. PMCATST: The PMCATST bit is used to configure the analog portion of the COMET for PMC's manufacturing tests. PMCATST is cleared when CSB is high and RSTB is low or when PMCATST is written as logic 0. PMCTST: The PMCTST bit is used to configure the COMET for PMC's manufacturing tests. When PMCTST is set to logic 1, the COMET microprocessor port becomes the test access port used to run the PMC manufacturing test vectors. The PMCTST bit is logically "ORed" with the IOTST bit, and is cleared by setting CSB high. DBCTRL: The DBCTRL bit is used to pass control of the data bus drivers to the CSB pin. When the DBCTRL bit is set to logic 1, the CSB pin controls the output enable for the data bus. While the DBCTRL bit is set, holding the CSB pin
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COMBINED E1/T1 TRANSCEIVER
high causes the COMET to drive the data bus and holding the CSB pin low tri-states the data bus. The DBCTRL bit overrides the HIZDATA bit. The DBCTRL bit is used to measure the drive capability of the data bus driver pads. IOTST: The IOTST bit is used to allow normal microprocessor access to the test registers and control the test mode in each block in the COMET for board level testing. When IOTST is a logic 1, all blocks are held in test mode and the microprocessor may write to a block's test mode 0 registers to manipulate the outputs of the block and consequently the device outputs (refer to the "Test Mode 0 Details" in this section). HIZIO, HIZDATA: The HIZIO and HIZDATA bits control the tri-state modes of the COMET . While the HIZIO bit is a logic 1, all output pins of the COMET except the data bus are held in a high-impedance state. The microprocessor interface is still active. While the HIZDATA bit is a logic 1, the data bus is also held in a highimpedance state which inhibits microprocessor read cycles.
12.1 Test Mode 0
In test mode 0, the COMET allows the logic levels on the device inputs to be read through the microprocessor interface, and allows the device outputs to be forced to either logic level through the microprocessor interface. To enable test mode 0, the IOTST bit in the Master Test Register (register 00BH) must be set to logic 1 and the following addresses must be written with 00H: 101H, 111H, 115H, 119H, 11DH, 121H, 125H, 129H, 131H, 139H, 141H, 149H, 14DH, 151H, 155H, 157H, 159H, 161H, 165H, 167H, 169H, 16BH, 16DH, 171H, 179H, 181H, 18DH, 191H, 1A9H, 1B1H, 1B9H, 1C1H, 1C9H, 1D1H, 1D7H, 1E1H, 1F1H and 1F9H. All other registers must be in their default (i.e., reset) state, except as noted below. Reading the following address locations returns the values for the indicated inputs:
Table 73 Addr
114H 118H
- Observing Inputs in Test Mode 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2
RCLKI TCLKI
1
Bit 1
Bit 0
RDAT
1
2
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COMBINED E1/T1 TRANSCEIVER
133H 134H 143H 1D6H 1F0H TRIMF BRCLK BTCLK BTFP BTSIG
BRFP
BTPCM XCLK
Writing the following address locations forces the outputs to the value in the corresponding bit position:
Table 74 Addr
100H 118H 11AH 133H 143H 144H BRPCM BRSIG INT
4
- Controlling Outputs in Test Mode 0 Bit 7
RSYNC TFP TCLKO BRPCM (OEB) BRSIG (OEB) BRFP BRFP (OEB)
3 3
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TDAT
3
BRCLK
BRCLK (OEB)
BTCLK (OEB)
BTCLK
BTFP (OEB)
BTFP
Notes:
1. To observe the value of RCLKI or RDAT, the RUNI bit in the Receive Line Interface Configuration register must be set to logic 1 and the RJATBYP bit in the Receive Options register must be set to logic 0. Additionally, the value on RDAT must be clocked in by RCLKI (one clock pulse) in order to be read. 2. To observe the value of TCLKI, the PLLREF1 and PLLREF0 bits in the Transmit Timing Options register must both be set to logic 1. 3. To control the TFP, TDAT and TCLKO outputs, the TJATBYP bit in the Transmit Options register must be set to logic 0 and the TUNI bit in the Transmit Line Interface Configuration register must be set to logic 1. Additionally, the value written to the TDAT and TFP bits do not propagate to the TDAT and TFP outputs, respectively, until the TCLKO output is toggled twice (i.e., by setting the TCLKO bit to logic 0, logic 1, logic 0, logic 1 and back to logic 0).
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PM4351 COMET
COMBINED E1/T1 TRANSCEIVER
4. Writing a logic 1 to the block interrupt signal INT at address 143H, asserts the INTB output low. In order to force INTB to the high impedance state, registers, 110H to 1FFH must be initialized to 00H. 5. The "signal_name (OEB)" signals will set the corresponding output signal, "signal_name", to high impedance when set high. 6. The "signal_name (OEB)" signals will set the corresponding bidirectional signal, "signal_name", to an output when set low.
12.2 JTAG Test Port
The COMET JTAG Test Access Port (TAP) allows access to the TAP controller and the 4 TAP registers: instruction, bypass, device identification and boundary scan. Using the TAP, device input logic levels can be read, device outputs can be forced, the device can be identified and the device scan path can be bypassed. For more details on the JTAG port, please refer to the Operations section.
Instruction Register Length - 3 bits Instructions Selected Register Instruction Codes, IR[2:0]
EXTEST IDCODE SAMPLE BYPASS BYPASS STCTEST BYPASS BYPASS
Boundary Scan Identification Boundary Scan Bypass Bypass Boundary Scan Bypass Bypass
000 001 010 011 100 101 110 111
Identification Register
Length - 32 bits Version number - 5H for Rev G and F, 4H for Rev E Part Number - 4351H
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COMBINED E1/T1 TRANSCEIVER
Manufacturer's identification code - 0CDH Device identification - 543510CDH for Rev. G and F, 443510CDH for Rev. E
Table 75
- Boundary Scan Register
Length - 59 bits Pin/ Enable Scan Register Bit Pin/ Enable Scan Register Bit Pin/ Enable Scan Register Bit
HIZ 3,4 XCLK TCLKI TCLKO TDAT TFP BTCLK BTCLK_OEB 1 BTPCM BTSIG BTFP BTFP_OEB 1 CSB RSTB RDB WRB INTB D0 DO_OEB 1 D1
58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39
D1_OEB 1 D2 D2_OEB 1 D3 D3_OEB 1 D4 D4_OEB 1 D5 D5_OEB 1 D6 D6_OEB 1 D7 D7_OEB 1 A0 A1 A2 A3 A4 A5 A6
38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19
A7 A8 ALE BRFP BRFP_OEB 1 BRSIG BRSIG_OEB BRPCM BRPCM_OEB 2 BRCLK BRCLK_OEB 1 RSYNC RCLKI RCLKI_OEB 1 RDAT RDAT_OEB 1 TRIMF NC NC_OEB
18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
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COMBINED E1/T1 TRANSCEIVER
Notes:
1. These OEB signals, when set low, will set the corresponding bidirectional signal to an output. 2. These OEB signals, when set high, will set the corresponding output to high impedance. 3. When set high, TCLKO, TDAT, TFP, and RSYNC will be set to high impedance. 4. HIZ is the first bit in the boundary scan chain.
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PM4351 COMET
COMBINED E1/T1 TRANSCEIVER
13 13.1
FUNCTIONAL TIMING Transmit Backplane Interface
By convention, the first bit transmitted in each timeslot is designated bit 0; the last is bit 7.
Figure 13 - Transmit Backplane: CMS=0, FE=1, DE=1, BTFP is Input
BTCLK BTFP BTPCM
F-bit
Figure 14 - Transmit Backplane: CMS=0, FE=1, DE=0, BTFP is Input
BTCLK BTFP BTPCM
F-bit
Figure 15 - Transmit Backplane: CMS=1, FE=1, DE=1, BTFP is Input
BTCLK BTFP BTPCM
F-bit
Figure 16 - Transmit Backplane: CMS=1, FE=0, DE=1, BTFP is Input
BTCLK BTFP BTPCM
F-bit
Figure 13, Figure 14, Figure 15, and Figure 16 above indicate the relationship between BTCLK, BTFP, and BTPCM with various settings for the BTIF's CMS, FE, and DE register bits in T1 mode with BTFP configured as an input (FPMODE=1). When FE and DE have the same value, the frame pulse is sampled on the same clock edge as the data. When FE and DE have opposite values, the frame pulse is sampled one clock edge before the data. In the above figures, the TSOFF[6:0], BOFF_EN and BOFF[2:0] register bits are logic zero.
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PM4351 COMET
COMBINED E1/T1 TRANSCEIVER
Figure 17 - Transmit Backplane: CMS=0, FE=1, DE=1, BTFP is Output
BTCLK
BTFP BTPCM
F-bit
Figure 18 - Transmit Backplane: CMS=0, FE=1, DE=0, BTFP is Output
1
BTCLK
2
3
BTFP BTPCM
F-bit
Figure 17 and Figure 18 above indicate the relationship between BTCLK, BTFP, and BTPCM with two settings for the BTIF's CMS, FE, and DE register bits in T1 mode with BTFP configured as an output (FPMODE=0). When FE and DE have the same value, the frame pulse is updated on the same clock edge as the data is sampled. When FE and DE have opposite values, the frame pulse is updated three clock edge before the data is sampled. In the above figures, the TSOFF[6:0], BOFF_EN and BOFF[2:0] register bits are logic zero.
Figure 19
BTFP
- Transmit Backplane at 1.544 Mbit/s (T1 mode)
1.544 MHz BTCLK (CM S = 0)
BTPCM
7
0
1
2
3
4
5
6
7
F
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
BTSIG
D
X
A
B
C
D
X
A
B
C
D
X
A
B
C
D
Time Slot 23
F-bit or parity
Time Slot 0
Time Slot 1
A 1.544 Mbit/s backplane in T1 mode is configured by setting RATE[1:0] of the Transmit Backplane Configuration register to 'b00 and the E1/T1B bit of the Global Configuration register to a logic 0. In Figure 19, BTFP, BTPCM and BTSIG are configured to be updated on the falling edge of BTCLK by setting FE and DE bits of the Transmit Backplane Configuration register to logic 0. The TSOFF[6:0], BOFF_EN and BOFF[2:0] register bits are all logic 0, therefore BTFP is expected to be aligned to the first bit of the frame. A 1.544 Mbit/s backplane in T1 mode is configured by setting the RATE[1:0] bits of the Transmit Backplane Configuration register to 'b00 and the E1/T1B bit of
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PM4351 COMET
COMBINED E1/T1 TRANSCEIVER
the Global Configuration register to a logic 0. Once the RATE[1:0] bits are set, a reset is required to change to a new RATE[1:0]. In Figure 19, BTPCM and BTFP are configured to be sampled on the falling edge of BTCLK by setting the DE and FE bits of the Transmit Backplane Configuration register to a logic 0. The TSOFF[6:0], BOFF_EN and BOFF[2:0] register bits are all logic zero; therefore, BTFP is expected to be aligned to the F-bit position.
Figure 20
BTFP 2.048 MHz BTCLK (CMS = 0) 4.096 MHz BTCLK (CMS = 1)
- Transmit Backplane at 2.048 Mbit/s (T1 mode)
BTPCM
7
0
1
2
3
4
5
6
7
F-bit
X
0
1
2
3
4
5
6
7
0
BTSIG
D
X
A
B
C
D
X
X
A
B
C
D
X
Time Slot 31 (used)
Time Slot 0 (unused)
Time Slot 1 (used)
A 2.048 Mbit/s backplane in T1 mode is configured by setting the RATE[1:0] bits of the Transmit Backplane Configuration register to 'b01 and the E1/T1B bit of the Global Configuration register to a logic 0. In Figure 20, BTFP, BTPCM and BTSIG are configured to be sampled on the rising edge of BTCLK by setting the FE and DE bits of the Transmit Backplane Configuration register to logic 1. Once the RATE[1:0] bits are set, a reset is required to change to a new RATE[1:0]. In Figure 20, the MAP bit of the Transmit Backplane Frame Pulse Configuration register is a logic 0. Therefore, every fourth time slot is unused, starting with timeslot 0. The framing bit is sampled during bit 0 of time slot 0, so that only bits 1 to 7 of time slot 0 are ignored. If MAP is logic 1, the 24 T1 channels would be nd aligned to the first 24 timeslots with the F-bit located in the last bit of the 32 timeslot. The TSOFF[6:0], BOFF_EN and BOFF[2:0] register bits are all logic zero; therefore, BTFP is expected to be aligned to the F-bit position.
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COMBINED E1/T1 TRANSCEIVER
Figure 21
BTFP
- Transmit Backplane at 2.048 Mbit/s (E1 mode)
2.048 MHz BTCLK (CM S = 0)
4.096 MHz BTCLK (CM S = 1)
BTPCM
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
BTSIG
D
X
A
B
C
D
X
X
A
B
C
D
X
Time Slot 31
Time Slot 0
Time Slot 1
A 2.048 Mbit/s backplane in E1 mode is configured by setting the RATE[1:0] bits of the Transmit Backplane Configuration register to 'b01 and the E1/T1B bit of the Global Configuration register to a logic 1. In Figure 21, BTFP, BTPCM and BTSIG are configured to be sampled on the rising edge of BTCLK by setting the FE and DE bits of the Transmit Backplane Configuration register to logic 1. Once the RATE[1:0] bits are set, a reset is required to change to a new RATE[1:0]. The TSOFF[6:0], BOFF_EN and BOFF[2:0] register bits are all logic zero; therefore, BTFP is expected to be aligned to the first bit of the frame.
Figure 22
BTFP
4. 096 MHz BTCLK (CMS = 0)
- Transmit Backplane at 4.096 Mbit/s (T1 mode)
BTPCM TS 31 BTSIG
C D
X
F
X TS 0
X
TS 1
X
TS 2
X
X
X
X
X
A
B
C
D
X
X
A
B
C
D
X
A 4.096 Mbit/s backplane in T1 mode is configured by setting the RATE[1:0] bits of the Transmit Backplane Configuration register to 'b10 and the E1/T1B bit of the Global Configuration register to a logic 0. In Figure 20, BTFP, BTPCM and BTSIG are configured to be sampled on the rising edge of BTCLK by setting the FE and DE bits of the Transmit Backplane Configuration register to logic 1. TSOFF[6:0] is set to 'b0000000 so that the first of the two interleaved bytes is sampled. Once the RATE[1:0] bits are set, a reset is required to change to a new RATE[1:0]. In Figure 20, the MAP bit of the Transmit Backplane Frame Pulse Configuration register is a logic 0. Therefore, every fourth time slot is unused, starting with timeslot 0. The framing bit is sampled during bit 0 of time slot 0, so that only bits 1 to 7 of time slot 0 are ignored. If MAP is logic 1, the 24 T1 channels would be nd aligned to the first 24 timeslots with the F-bit located in the last bit of the 32 timeslot.
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PM4351 COMET
COMBINED E1/T1 TRANSCEIVER
Figure 23
BTFP
4. 096 MHz BTCLK (CMS = 0)
- Transmit Backplane at 4.096 Mbit/s (E1 mode)
BTPCM TS 31 BTSIG
C D
X
TS 0
X
TS 1
X
TS 2
X
X
X
X
X
A
B
C
D
X
X
A
B
C
D
X
A 4.096 Mbit/s backplane in E1 mode is configured by setting the RATE[1:0] bits of the Transmit Backplane Configuration register to 'b10 and the E1/T1B bit of the Global Configuration register to a logic 1. In Figure 23, BTFP, BTPCM and BTSIG are configured to be sampled on the rising edge of BTCLK by setting the FE and DE bits of the Transmit Backplane Configuration register to logic 1. TSOFF[6:0] is set to 'b0000000 so that the first of the two interleaved bytes is sampled.
Figure 24 - Transmit Backplane at 8.192 Mbit/s (T1 mode)
BTFP
8. 192 MHz BTCLK (CMS = 0)
BTPCM BTSIG
X
F
X TS 0
X
X
X
TS 1
X
X
X
X
X
X
X
X
X
ABCD
X
X
X
A 8.192 Mbit/s backplane in T1 mode is configured by setting the RATE[1:0] bits of the Transmit Backplane Configuration register to 'b11 and the E1/T1B bit of the Global Configuration register to a logic 0. In Figure 24, BTFP, BTPCM and BTSIG are configured to be sampled on the rising edge of BTCLK by setting the FE and DE bits of the Transmit Backplane Configuration register to logic 1. TSOFF[6:0] is set to 'b0000000 so that the first of the four interleaved bytes is sampled. Once the RATE[1:0] bits are set, a reset is required to change to a new RATE[1:0]. In Figure 24, the MAP bit of the Transmit Backplane Frame Pulse Configuration register is a logic 0. Therefore, every fourth time slot is unused, starting with timeslot 0. The framing bit is sampled during bit 0 of time slot 0, so that only bits 1 to 7 of time slot 0 are ignored. If MAP is logic 1, the 24 T1 channels would be nd aligned to the first 24 timeslots with the F-bit located in the last bit of the 32 timeslot.
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COMBINED E1/T1 TRANSCEIVER
Figure 25
BTFP
8. 192 MHz BTCLK (CMS = 0)
- Transmit Backplane at 8.192 Mbit/s (E1 mode)
BTPCM BTSIG
X
TS 0
X
X
X
TS 1
X
X
X
X
X
X
X
X
X
ABCD
X
X
X
A 8.192 Mbit/s backplane in E1 mode is configured by setting the RATE[1:0] bits of the Transmit Backplane Configuration register to 'b11 and the E1/T1B bit of the Global Configuration register to a logic 1. In Figure 25, BTFP, BTPCM and BTSIG are configured to be sampled on the rising edge of BTCLK by setting the FE and DE bits of the Transmit Backplane Configuration register to logic 1. TSOFF[6:0] is set to 'b0000000 so that the first of the four interleaved bytes is sampled.
Figure 26
BTC LK
- Concentration Highway Interface Timing, Example 1
1 2 3 4 5 6 7 8 9 10 11 12
BTFP
CER = 4
BTPC M
bit 5 TS 31
bit 6 TS 3 1
bit 7 TS 31
bit 0 TS 0
bit 1 TS 0
bit 2 TS 0
bit 3 TS 0
bit 4 TS 0
bit 5 TS 0
bit 6 TS 0
bit 7 TS 0
bit 0 TS 1
CHI timing is configured by setting the BOFF_EN bit of the Transmit Backplane Bit Offset register to a logic 1. In Figure 26, the DE and FE register bits are set to logic 0 so that BTPCM, BTSIG and BTFP are sampled on the falling edge of BTCLK. CMS is set to logic 0 so that the clock rate is equal to the data rate. BOFF[2:0] is set to 'b000 so that the receive clock edge (CER) is equal to 4 (as determined by the table in the Transmit Backplane Bit Offset register description of BOFF[2:0]) and BTPCM is sampled 4 clock edges after BTFP is sampled. TSOFF is set to 'b0000000 so that there is no time slot offset.
Figure 27
BTC LK
- Concentration Highway Interface Timing, Example 2
1 2 3 4 5 6 7 8 9 10 11 12
BTFP
CER = 11
BTPC M
bit 5 TS 31
bit 6 TS 31
bit 7 TS 31
bit 0 TS 0
bit 1 TS 0
bit 2 TS 0
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PM4351 COMET
COMBINED E1/T1 TRANSCEIVER
CHI timing is configured by setting the BOFF_EN bit of the Transmit Backplane Bit Offset register to a logic 1. In Figure 27, the FE register bit is set to logic 1 so that BTFP is sampled on the rising edge of BTCLK. The DE register bit is set to logic 0 so that BTPCM is sampled on the falling edge of BTCLK. CMS is set to logic 1 so that the clock rate is equal to two times the data rate. BOFF[2:0] is set to 'b001 so that the receive clock edge (CER) is equal to 11 (as determined by the table in the Transmit Backplane Bit Offset register description of BOFF[2:0]) and BTPCM is sampled 11 clock edges after BTFP is sampled. TSOFF is set to 'b0000000 so that there is no time slot offset.
13.2 Receive Backplane Interface
By convention, the first bit transmitted in each timeslot shall be designated bit 0; the last shall be bit 7.
Figure 28
BRFP
- Receive Backplane at 1.544 Mbit/s (T1 Mode)
1.544 M Hz BRCLK (CM S = 0)
BRPCM
7
0
1
2
3
4
5
6
7
F
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
BRSIG
D
X
A
B
C
D
X
A
B
C
D
X
A
B
C
D
Tim e Slot 23
F-bit or parity
Tim e Slot 0
Tim e Slot 1
A 1.544 Mbit/s backplane in T1 mode is configured by setting the RATE[1:0] bits of the Receive Backplane Configuration register to 'b00 and the E1/T1B bit of the Global Configuration register to a logic 0. In Figure 28, BRFP, BRPCM and BRSIG are configured to be sampled on the falling edge of BRCLK by setting the FE and DE bits of the Receive Backplane Configuration register to logic 0. The TSOFF[6:0], BOFF_EN and BOFF[2:0] register bits are all logic zero; therefore, BRFP is aligned to the first bit of the frame. Once the RATE[1:0] bits are set, a reset is required to change to a new RATE[1:0].
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PM4351 COMET
COMBINED E1/T1 TRANSCEIVER
Figure 29
BRFP 2.048 MHz BRCLK (CMS = 0) 4.096 MHz BRCLK (CMS = 1)
- Receive Backplane at 2.048 Mbit/s (T1 Mode)
BRPCM
7
0
1
2
3
4
5
6
7
F
X
0
1
2
3
4
5
6
7
0
BRSIG
D
X
A
B
C
D
X
X
A
B
C
D
X
Time Slot 31 (used)
Time Slot 0 (unused)
Time Slot 1 (used)
A 2.048 Mbit/s backplane in T1 mode is configured by setting the RATE[1:0] bits of the Receive Backplane Configuration register to 'b01 and the E1/T1B bit of the Global Configuration register to a logic 0. In Figure 29, BRFP, BRPCM and BRSIG are configured to be updated on the falling edge of BRCLK by setting the FE and DE bits of the Receive Backplane Configuration register to logic 0. Once the RATE[1:0] bits are set, a reset is required to change to a new RATE[1:0]. In Figure 29, the MAP register bit is logic 0. As shown, every fourth time slot is unused, starting with the first. If MAP is a logic 1, time slots 0 through 23 would be used. The framing bit is presented during bit 0 of time slot 0, so that only bits 1 to 7 of time slot 0 are ignored. The TSOFF[6:0], BOFF_EN and BOFF[2:0] register bits are all logic zero; therefore, BRFP is expected to be aligned to the first bit of the frame.
Figure 30
BRFP 2.048 MHz BRCLK (CMS = 0) 4.096 MHz BRCLK (CMS = 1)
- Receive Backplane at 2.048 Mbit/s (E1 Mode)
BRPCM
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
BRSIG
D
X
A
B
C
D
X
A
B
C
D
X
Time Sl ot 31
Time Slot 0
Time Slot 1
A 2.048 Mbit/s backplane in E1 mode is configured by setting the RATE[1:0] bits of the Receive Backplane Configuration register to 'b01 and E1/T1B bit of the Global Configuration register to logic 1. In Figure 30, BRFP, BRPCM and BRSIG are configured to be updated on the falling edge of BRCLK by setting the FE and DE bits of the Receive Backplane Configuration register to logic 0. The TSOFF[6:0], BOFF_EN and BOFF[2:0] register bits are all logic zero; therefore,
PROPRIETARY AND CONFIDENTIAL
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PM4351 COMET
COMBINED E1/T1 TRANSCEIVER
BRFP is expected to be aligned to the first bit of the frame. Once the RATE[1:0] bits are set, a reset is required to change to a new RATE[1:0].
Figure 31
BRFP
4. 096 MHz BRCLK (CMS = 0)
- Receive Backplane at 4.096 Mbit/s (T1 Mode)
BRPCM BRSIG
A
TS 30
TS 31
F
X TS 0
TS 1
B
C
D
X
A
B
C
D
X
X
A
B
C
D
A 4.096 Mbit/s backplane in T1 mode is configured by setting the RATE[1:0] bits of the Receive Backplane Configuration register to 'b10 and the E1/T1B bit of the Global Configuration register to logic 0. In Figure 31, BRFP, BRPCM and BRSIG are configured to be updated on the falling edge of BRCLK by setting the FE and DE bits of the Receive Backplane Configuration register to logic 0. TSOFF[6:0] is set to 'b0000000 so that the first of the two interleaved bytes is sampled. Once the RATE[1:0] bits are set, a reset is required to change to a new RATE[1:0]. In Figure 31, the MAP register bit is logic 0. As shown, every fourth time slot is unused, starting with the first. If MAP is a logic 1, time slots 0 through 23 would be used. The framing bit is presented during bit 0 of time slot 0, so that only bits 1 to 7 of time slot 0 are ignored. The TSOFF[6:0], BOFF_EN and BOFF[2:0] register bits are all logic zero; therefore, BRFP is expected to be aligned to the first bit of the frame.
Figure 32
BRFP
4. 096 MHz BRCLK (CMS = 0)
- Receive Backplane at 4.096 Mbit/s (E1 Mode)
BRPCM BRSIG
A
TS 30
TS 31
TS 0
TS 1
B
CD
X
A
B
C
D
X
X
A
B
C
D
A 4.096 Mbit/s backplane in E1 mode is configured by setting the RATE[1:0] bits of the Receive Backplane Configuration register to 'b10 and the E1/T1B bit of the Global Configuration register to logic 1. In Figure 32, BRFP, BRPCM and BRSIG are configured to be updated on the falling edge of BRCLK by setting the FE and DE bits of the Receive Backplane Configuration register to logic 0. TSOFF[6:0] is set to 'b0000000 so that the first of the two interleaved bytes is sampled. Once the RATE[1:0] bits are set, a reset is required to change to a new RATE[1:0].
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PM4351 COMET
COMBINED E1/T1 TRANSCEIVER
Figure 33
BRFP
8. 192 MHz BRCLK (CMS = 0)
- Receive Backplane at 8.192 Mbit/s (T1 Mode)
BRPCM BRSIG
TS 31
F
X TS 0
X
AB CD
X
A 8.192 Mbit/s backplane in T1 mode by setting the RATE[1:0] bits of the Receive Backplane Configuration register to 'b11 and the E1/T1B bit of the Global Configuration register to a logic 0. In Figure 24, BRFP, BRPCM and BRSIG are configured to be updated on the falling edge of BRCLK by setting the FE and DE bits of the Receive Backplane Configuration register to logic 0. TSOFF[6:0] is set to 'b0000000 so that the first of the four interleaved bytes is sampled. Once the RATE[1:0] bits are set, a reset is required to change to a new RATE[1:0]. In Figure 24, the MAP register bit is logic 0. As shown, every fourth time slot is unused, starting with the first. If MAP is a logic 1, time slots 0 through 23 would be used. The framing bit is presented during bit 0 of time slot 0, so that only bits 1 to 7 of time slot 0 are ignored. The TSOFF[6:0], BOFF_EN and BOFF[2:0] register bits are all logic zero; therefore, BRFP is expected to be aligned to the first bit of the frame.
Figure 34
BRFP
8. 192 MHz BRCLK (CMS = 0)
- Receive Backplane at 8.192 Mbit/s (E1 Mode)
BRPCM BRSIG
TS 31
TS 0
X
ABCD
X
A 8.192 Mbit/s backplane in E1 mode by setting the RATE[1:0] bits of the Receive Backplane Configuration register to 'b11 and the E1/T1B bit of the Global Configuration register to a logic 1. In Figure 34, BRFP, BRPCM and BRSIG are configured to be updated on the falling edge of BRCLK by setting the FE and DE bits of the Receive Backplane Configuration register to logic 0. TSOFF[6:0] is set to 'b0000000 so that the first of the four interleaved bytes is sampled.
PROPRIETARY AND CONFIDENTIAL
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PM4351 COMET
COMBINED E1/T1 TRANSCEIVER
Figure 35
BRC LK
- Concentration Highway Interface Timing, Example 1
1 2 3 4 5 6 7 8 9 10 11 12
BRFP
CER = 3
BRPCM
bit 5 TS 3 1
bit 6 TS 3 1
bit 7 TS 31
bit 0 TS 0
bit 1 TS 0
bit 2 TS 0
bit 3 TS 0
bit 4 TS 0
bit 5 TS 0
bit 6 TS 0
bit 7 TS 0
bit 0 TS 1
CHI timing is configured by setting the BOFF_EN bit of the Receive Backplane Configuration register to a logic 1. In Figure 35, FE is set to logic 0 so that BRFP is sampled on the falling edge of BRCLK. DE is set to logic 1 so that BRPCM is updated on the rising edge of BRCLK. CMS is set to logic 0 so that the clock rate is equal to the data rate. BOFF[2:0] is set to 'b000 so that the transmit clock edge (CET) is equal to 3 (as determined by the table in the register description of BOFF[2:0]) and BRPCM is updated 3 clock edges after BRFP is sampled. TSOFF is set to 'b0000000 so that there is no time slot offset.
Figure 36
BRCLK
- Concentration Highway Interface Timing, Example 2
1 2 3 4 5 6 7 8 9 10 11 12
BRFP
CER = 8
BRPCM
bit 5 TS 31
Don't Care
bit 6 TS 31
Don't Care
bit 7 TS 31
Don't Care
bit 0 TS 0
Don't Care
bit 1 TS 0
Don't Care
bit 2 TS 0
CHI timing is configured by setting BOFF_EN to a logic 1. In Figure 36, FE is set to logic 1 so that BRFP is sampled on the rising edge of BRCLK. DE is set to logic 1 so that BRPCM is updated on the rising edge of BRCLK. CMS is set to logic 1 so that the clock rate is equal to two times the data rate. BOFF[2:0] is set to 'b001 so that the transmit clock edge (CET) is equal to 8 (as determined by the table in the register description of BOFF[2:0]) and BRPCM is updated 8 clock edges after BRFP is updated. TSOFF is set to 'b0000000 so that there is no time slot offset.
PROPRIETARY AND CONFIDENTIAL
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PM4351 COMET
COMBINED E1/T1 TRANSCEIVER
14 14.1
OPERATION Configuring the COMET from Reset
After a system reset (either via the RSTB pin or via the RESET register bit), the COMET will default to the following settings:
Table 76 Setting - Default Settings Receiver Section Transmitter Section
Framing Format Line Code Line interface
T1 SF B8ZS Pins RXTIP and RXRING active short haul analog inputs * 1.544 Mbit/s data rate * BRPCM, BRSIG high impedance * BRFP and BRCLK configured as inputs
T1 SF AMI TXTIP[1:0], TXRING[1:0], TCLKO, TDAT and TFP held low * 1.544 Mbit/s data rate * BTPCM active * BTSIG inactive * BTFP and BTCLK configured as inputs disabled * TX-ELST bypassed * Signaling alignment disabled * F, CRC, FDL bit bypass disabled
System Backplane
Data Link Options
disabled * RX-ELST not bypassed * PMON accumulates OOFs (not COFAs)
Timing Options
Not applicable
Jitter attenuation enabled, with TCLKO referenced to BTCLK All diagnostic modes disabled
Diagnostics
All diagnostic modes disabled
To configure the COMET for ESF framing format, after a reset, the following registers should be written with the indicated values:
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PM4351 COMET
COMBINED E1/T1 TRANSCEIVER
Table 77 Action
- ESF Frame Format Addr Data Effect
Write CDRC Configuration Register Write RX-ELST Configuration Register Write TX-ELST Configuration Register Write T1 XBAS Configuration Register
10H 1CH 20H 54H
00H 00H 00H 3XH
Select B8ZS line code for receiver Select 193-bit frame format. Select 193-bit frame format. Select B8ZS, enable for ESF in transmitter (bits defined by 'X' determine the FDL data rate & Zero Code suppression algorithm used) Select ESF, 2 of 4 OOF threshold Select ESF, 2 of 5 OOF threshold Select ESF, 2 of 6 OOF threshold (bits defined by 'X' determine the FDL data rate, should be same as those written to XBAS)
Write T1 FRMR Configuration Register
48H
1XH or 5XH or 9XH
Write RBOC Enable Register
6AH
00H or 02H 1XH
Enable 8 out of 10 validation Enable 4 out of 5 validation Select ESF (bits defined by 'X' determine the ESF Yellow data rate, should be same as those written to T1 FRMR) Enable Inband Code detection Program Loopback Activate Code pattern Program Loopback Deactivate Code pattern Select ESF
Write ALMI Configuration Register
60H
Write IBCD Configuration Register Write IBCD Activate Code Register Write IBCD Deactivate Code Register Write SIGX Configuration Register
4CH 4EH 4FH 50H
00H 08H 44H 04H
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PM4351 COMET
COMBINED E1/T1 TRANSCEIVER
To configure the COMET for SLC(R)96 framing format, after a reset, the following registers should be written with the indicated values:
Table 78 Action - SLC(R)96 Frame Format Addr Data Effect
Write CDRC Configuration Register Write RX -ELST Configuration Register Write TX-ELST Configuration Register Write T1 XBAS Configuration Register Write T1 FRMR Configuration Register
10H 1CH 20H 54H 48H
80H 00H 00H 08H 08H or 48H or 88H
Select AMI line code for receiver Select 193-bit frame format. Select 193-bit frame format. Select AMI, enable for SLC(R)96 in transmitter Select SLC(R)96, 2 of 4 OOF threshold Select SLC(R)96, 2 of 5 OOF threshold Select SLC(R)96, 2 of 6 OOF threshold Select SLC(R)96 Enable Inband Code detection Program Loopback Activate Code pattern Program Loopback Deactivate Code pattern Select SLC(R)96
Write ALMI Configuration Register Write IBCD Configuration Register Write IBCD Activate Code Register Write IBCD Deactivate Code Register Write SIGX Configuration Register
60H 4CH 4EH 4FH 50H
08H 00H 08H 44H 00H
To configure the COMET for SF framing format, after a reset, the following registers should be written with the indicated values:
PROPRIETARY AND CONFIDENTIAL
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PM4351 COMET
COMBINED E1/T1 TRANSCEIVER
Table 79 Action
- SF Frame Format Addr Data Effect
Write CDRC Configuration Register Write RX-ELST Configuration Register Write TX-ELST Configuration Register Write T1 XBAS Configuration Register Write T1 FRMR Configuration Register
10H 1CH 20H 54H 48H
80H 00H 00H 00H 00H or 40H or 80H
Select AMI line code for receiver Select 193-bit frame format. Select 193-bit frame format. Select AMI, enable for SF in transmitter Select SF, 2 of 4 OOF threshold Select SF, 2 of 5 OOF threshold Select SF, 2 of 6 OOF threshold Select SF Enable Inband Code detection Program Loopback Activate Code pattern Program Loopback Deactivate Code pattern Select SF
Write ALMI Configuration Register Write IBCD Configuration Register Write IBCD Activate Code Register Write IBCD Deactivate Code Register Write SIGX Configuration Register
60H 4CH 4EH 4FH 50H
00H 00H 08H 44H 00H
To configure the COMET for T1DM framing format, after a reset, the following registers should be written with the indicated values:
Table 80 Action - T1DM Frame Format Addr Data Effect
Write CDRC Configuration Register
10H
80H
Select AMI line code for receiver
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PM4351 COMET
COMBINED E1/T1 TRANSCEIVER
Action
Addr
Data
Effect
Write RX-ELST Configuration Register Write TX-ELST Configuration Register Write T1 XBAS Configuration Register Write T1 FRMR Configuration Register Write ALMI Configuration Register
1CH 20H 54H
00H 00H 04H or 0CH 04H 04H or 0CH
Select 193-bit frame format. Select 193-bit frame format. Select AMI, enable for T1DM in transmitter Select T1DM, 4 of 12 OOF threshold Select T1DM with standard Red integration Select T1DM with alternate Red integration Enable Inband Code detection Program Loopback Activate Code pattern Program Loopback Deactivate Code pattern Select T1DM
48H 60H
Write IBCD Configuration Register Write IBCD Activate Code Register Write IBCD Deactivate Code Register Write SIGX Configuration Register
Table 81 Action
4CH 4EH 4FH 50H
00H 08H 44H 00H
- E1 Frame Format Addr Data Effect
Write Global Configuration Register Write RXCE Receive Data Link 1 Control Register Write TXCI Transmit Data Link 1 Control Register Write E1 TRAN Configuration Register Write E1 FRMR Frame Alignment Options Register
00H 028H 038H 80H 90H
01H 00H 00H 70H 80H
Select E1 mode. Disable extraction of T1 data link for HDLC receiver #1. Disable insertion of T1 data link from HDLC transmitter #1. Enable CRC multiframe generation Enable CRC multiframe search algorithm
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PM4351 COMET
COMBINED E1/T1 TRANSCEIVER
To access the Performance Monitor Registers, the following polling sequence should be used:
Table 82 Action - PMON Polling Sequence Addr Offset Data Effect
Write PMON Framing Bit Error Count Register Read Framing Bit Error Count Read OOF/COFA/FEBE (LSB) Count Register
59H 59H 5AH
00H
Latch performance data into PMON registers Read Framing bit error count Read least significant byte outof-frame event count, change of frame alignment event count if CCOFA bit in COMET Receive Options Register is set, or FEBE if E1 Read most significant byte outof-frame event count, change of frame alignment event count if CCOFA bit in COMET Receive Options Register is set, or FEBE if E1 Read least significant byte of bit error event or CRC error count Read most significant byte of bit error event or CRC error count Read least significant byte of line code violation count Read most significant byte of line code violation count
Read OOF/COFA/FEBE (MSB) Count Register
5BH
Read BEE/CRCE Count (LSB) Register Read BEE/CRCE Count (MSB) Register Read LCV Count (LSB) Register Read LCV Count (MSB) Register
5CH
5DH
5EH 5FH
To configure the COMET to utilize the internal HDLC transmitter and receiver for processing the ESF facility data link, the following registers should be written with the indicated values:
PROPRIETARY AND CONFIDENTIAL
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STANDARD PRODUCT DATA SHEET PMC-1970624 ISSUE 10
PM4351 COMET
COMBINED E1/T1 TRANSCEIVER
Table 83 Action
- ESF FDL Processing Addr Data Effect
Write RXCE Receive Data Link 1 Control Register
028H
20H
Select extraction of ESF Facility Data Link for HDLC receiver #1. (COMET must be set up for ESF frame format.) Select insertion of ESF Facility Data Link from HDLC transmitter #1. (COMET must be set up for ESF frame format.)
Write TXCI Transmit Data Link 1 Control Register
038H
20H
14.2
Using the Internal HDLC Transmitters
It is important to note that the access rate to the TDPR registers is limited by the rate of the transmit clock. The TDPR registers should be accessed at a rate no faster than that of the transmit system clock. To properly initialize the transmit HDLC controllers in transmit basic frame alignment mode (FPTYP is logic 0), transmit multiframe alignment (FPTYP is logic 1) must be configured for at least one multiframe (i.e., for at least one multiframe period in frame pulse master mode or for at least one input frame pulse in frame pulse slave mode). After this initialization, the FPTYP can be set to any desired value. Upon reset, the TDPR should be disabled by setting the EN bit in the TDPR Configuration Register to logic 0 (default value). After making all initial configurations to the TDPR, the EN bit should be set to logic 1 to enable the TDPR and then the FIFOCLR bit should be set and then cleared to initialize the TDPR FIFO. The TDPR is now ready to transmit. To initialize the TDPR, the TDPR Configuration Register must be properly set. If FCS generation is desired, the CRC bit should be set to logic 1. If the block is to be used in interrupt driven mode, then interrupts should be enabled by setting the FULLE, OVRE, UDRE, and LFILLE bits in the TDPR Interrupt Enable register to logic 1. The TDPR operating parameters in the TDPR Upper Transmit Threshold and TDPR Lower Interrupt Threshold registers should be set to the desired values. The TDPR Upper Transmit Threshold sets the value at which the TDPR automatically begins the transmission of HDLC packets, even if no complete packets are in the FIFO. Transmission will continue until the current packet is transmitted and the number of bytes in the TDPR FIFO falls to, or below, this threshold level. The TDPR will always transmit all complete HDLC
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PM4351 COMET
COMBINED E1/T1 TRANSCEIVER
packets (packets with EOM attached) in its FIFO. Finally, the TDPR can be enabled by setting the EN bit to logic 1. If no message is sent after the EN bit is set to logic 1, continuous flags will be sent. The TDPR can be used in a polled or interrupt driven mode for the transfer of packet data. In the polled mode the processor controlling the TDPR must periodically read the TDPR Interrupt Status register to determine when to write to the TDPR Transmit Data register. In the interrupt driven mode, the processor controlling the TDPR uses the INTB output to identify the interrupts which determine when writes can or must be done to the TDPR Transmit Data register.
14.2.1 Automatic transmission mode using interrupts:
The TDPR automatically transmits a packet once it is completely written into the TDPR FIFO. The TDPR also begins transmission of bytes once the FIFO level exceeds the programmable Upper Transmit Threshold. The CRC bit can be set to logic 1 so that the FCS is generated and inserted at the end of a packet. The TDPR Lower Interrupt Threshold should be set to such a value that sufficient warning of an underrun is given. The FULLE, LFILLE, OVRE, and UDRE bits are all set to logic 1 so an interrupt on INTB is generated upon detection of a FIFO full state, a FIFO depth below the lower limit threshold, a FIFO overrun, or a FIFO underrun. The following procedure should be followed to transmit HDLC packets: 1. Wait for data to be transmitted. Once data is available to be transmitted, go to step 2. 2. Write the data byte to the TDPR Transmit Data register. 3. If all bytes in the packet have been sent, set the EOM bit in the TDPR Configuration register to logic 1. Go to step 1. 4. If there are more bytes in the packet to be sent, go to step 2. While performing steps 1 to 4, the processor should monitor for interrupts generated by the TDPR. When an interrupt is detected, the TDPR Interrupt Routine should be executed. The TDPR will force transmission of the packet information when the FIFO depth exceeds the threshold programmed with the UTHR[6:0] bits in the TDPR Upper Transmit Threshold register. Transmission will not stop until the last byte of all complete packets is transmitted and the FIFO depth is at or below the threshold limit. The user should watch the FULLI and LFILLI interrupts to prevent overruns and underruns.
PROPRIETARY AND CONFIDENTIAL
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PM4351 COMET
COMBINED E1/T1 TRANSCEIVER
14.2.2 TDPR Interrupt Routine:
The following procedure should be carried out when an interrupt is detected on INT: 1. Read the TDPR Interrupt Status register. 2. If UDRI=1, then the FIFO has underrun and the last packet transmitted has been corrupted and needs to be retransmitted. When the UDRI bit transitions to logic 1, one Abort sequence and continuous flags will be transmitted. The TDPR FIFO is held in reset state. To re-enable the TDPR FIFO and to clear the underrun, the TDPR Interrupt Status/UDR Clear register should be written with any value. 3. If OVRI=1, then the FIFO has overflowed. The packet which the last byte written into the FIFO belongs to has been corrupted and must be retransmitted. Other packets in the FIFO are not affected. Either a timer can be used to determine when sufficient bytes are available in the FIFO or the user can wait until the LFILLI interrupt is set, indicating that the FIFO depth is at the lower threshold limit. If the FIFO overflows on the packet currently being transmitted (packet is greater than 128 bytes long), an Abort signal is scheduled to be transmitted, the FIFO is emptied, and then flags are continuously sent until there is data to be transmitted. The FIFO is held in reset until a write to the TDPR Transmit Data register occurs. This write contains the first byte of the next packet to be transmitted. 4. If OVRI=1, then the FIFO has overflowed. The packet which the last byte written into the FIFO belongs to has been corrupted and must be retransmitted. Other packets in the FIFO are not affected. When an overflow occurs, the OVR output signal is set. Either a timer can be used to determine when sufficient bytes are available in the FIFO or the user can wait until the LFILLI interrupt is set, indicating that the FIFO depth is at the lower threshold limit. The OVR output signal remains set until the next write to the TDPR Transmit Data register. This write contains the first byte of the next packet to be transmitted. If the FIFO overflows on the packet currently being transmitted (packet is greater than 128 bytes long), the OVR output signal is set, an Abort signal is scheduled to be transmitted, the FIFO is emptied, and then flags are continuously sent until there is data to be transmitted. The FIFO is held in reset until a write to the TDPR Transmit Data register occurs. This write contains the first byte of the next packet to be transmitted.
PROPRIETARY AND CONFIDENTIAL
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PM4351 COMET
COMBINED E1/T1 TRANSCEIVER
5. If FULLI=1 and FULL=1, then the TDPR FIFO is full and no further bytes can be written. When in this state, either a timer can be used to determine when sufficient bytes are available in the FIFO or the user can wait until the LFILLI interrupt is set, indicating that the FIFO depth is at the lower threshold limit. If FULLI=1 and FULL=0, then the TDPR FIFO had reached the FULL state earlier, but has since emptied out some of its data bytes and now has space available in its FIFO for more data. 6. If LFILLI=1 and BLFILL=1, then the TDPR FIFO depth is below its lower threshold limit. If there is more data to transmit, then it should be written to the TDPR Transmit Data register before an underrun occurs. If there is no more data to transmit, then an EOM should be set at the end of the last packet byte. Flags will then be transmitted once the last packet has been transmitted. If LFILLI=1 and BLFILL=0, then the TDPR FIFO had fallen below the lowerthreshold state earlier, but has since been refilled to a level above the lowerthreshold level.
14.2.3 Automatic transmission mode using polling:
The TDPR automatically transmits a packet once it is completely written into the TDPR FIFO. The TDPR also begins transmission of bytes once the FIFO level exceeds the programmable Upper Transmit Threshold. The CRC bit can be set to logic 1 so that the FCS is generated and inserted at the end of a packet. The TDPR Lower Interrupt Threshold should be set to such a value that sufficient warning of an underrun is given. The FULLE, LFILLE, OVRE, and UDRE bits are all set to logic 0 since packet transmission is set to work with a periodic polling procedure. The following procedure should be followed to transmit HDLC packets: 1. Wait until data is available to be transmitted, then go to step 2. 2. Read the TDPR Interrupt Status register. 3. If FULL=1, the TDPR FIFO is full and no further bytes can be written. Continue polling the TDPR Interrupt Status register until either FULL=0 or BLFILL=1. Then, go to either step 4 or 5 depending on implementation preference. 4. If BLFILL=1, the TDPR FIFO depth is below its lower threshold limit. Write the data into the TDPR Transmit Data register. Go to step 6.
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PM4351 COMET
COMBINED E1/T1 TRANSCEIVER
5. If FULL=0, the TDPR FIFO has room for at least 1 more byte to be written. Write the data into the TDPR Transmit Data register. Go to step 6. 6. If more data bytes are to be transmitted in the packet, go to step 2. 7. If all bytes in the packet have been sent, set the EOM bit in the TDPR Configuration register to logic 1. Go to step 1.
Figure 37 - Typical Data Frame
7
1
BIT: 8
0
6
1
5
1
4
1
3
1
2
1
1
0
FLAG
Address (high) (low) data bytes written to the Transmit Data Register and serially transmitted, bit 1 first
CONTROL
Frame Check Sequence 0 1 1 1 1 1 1 0
appended after EOM is set, if CRC is set
FLAG
14.3
Using the Internal HDLC Receivers
On power up of the system, the RDLC should be disabled by setting the EN bit in the Configuration Register to logic 0. The Interrupt Control Register should then be initialized to enable the INTB output and to select the FIFO buffer fill level at which an interrupt will be generated. If the INTE bit is not set to logic 1, the Status Register must be continuously polled to check the interrupt status (INTR) bit. After the Interrupt Control Register has been written, the RDLC can be enabled at any time by setting the EN bit in the Configuration Register to logic 1. When the RDLC is enabled, it will assume the link status is idle (all ones) and immediately begin searching for flags. When the first flag is found, an interrupt will be generated, and a dummy byte will be written into the FIFO buffer. This is done to provide alignment of link up status with the data read from the FIFO.
PROPRIETARY AND CONFIDENTIAL
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STANDARD PRODUCT DATA SHEET PMC-1970624 ISSUE 10
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COMBINED E1/T1 TRANSCEIVER
When an abort character is received, another dummy byte and link down status is written into the FIFO. This is done to provide alignment of link down status with the data read from the FIFO. It is up to the controlling processor to check the COLS Status Register bit for a change in the link status. If the COLS Status Register bit is set to logic 1, the FIFO must be emptied to determine the current link status. The first flag and abort status encoded in the PBS bits is used to set and clear a Link Active software flag. When the last byte of a properly terminated packet is received, an interrupt is generated. When the Status Register is read the PKIN bit will be logic 1. This can be a signal to the external processor to empty the bytes remaining in the FIFO or to just increment a number-of-packets-received count and wait for the FIFO to fill to a programmable level. Once the Status Register is read, the PKIN bit is cleared to logic 0 . If the Status Register is read immediately after the last packet byte is read from the FIFO, the PBS[2] bit will be logic 1 and the CRC and non-integer byte status can be checked by reading the PBS[1:0] bits. When the FIFO fill level is exceeded, an interrupt is generated. The FIFO must be emptied to remove this source of interrupt. The RDLC can be used in a polled or interrupt driven, or DMA-controlled mode for the transfer of frame data. In the polled mode, the INTB output is not used, and the processor controlling the RDLC must periodically read the Status Register of the RDLC to determine when to read the Data Register. In the interrupt driven mode, the processor controlling the RDLC uses the INTB output to determine when to read the Data Register. In the case of interrupt driven data transfer from the RDLC to the processor, the INTB output of the RDLC is connected to the interrupt input of the processor. Once the processor has determined the RDLC is the source of the interrupt, the interrupt service routine should process the data in the following order: 1. RDLC Status Register Read. If INTR=1 then proceed to step 2 else find the interrupt source elsewhere. 2. If OVR = 1, discard last frame and go to step 1. Overrun causes a reset of FIFO pointers. Any packets that may have been in the FIFO are lost. 3. If COLS = 1, set the EMPTY FIFO software flag. 4. If PKIN = 1, increment the PACKET COUNT. If the FIFO is desired to be emptied as soon as a complete packet is received, set the EMPTY FIFO software flag. If the EMPTY FIFO software flag is not set, FIFO emptying will be delayed until the FIFO fill level is exceeded. 5. Data Register Read.
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6. Status Register Read. 7. If OVR = 1, discard last frame and go to step 1. Overrun causes a reset of FIFO pointers. Any packets that may have been in the FIFO are lost. 8. If COLS = 1, set the EMPTY FIFO software flag. 9. If PKIN = 1, increment the PACKET COUNT. If the FIFO is desired to be emptied as soon as a complete packet is received, set the EMPTY FIFO software flag. If the EMPTY FIFO software flag is not set, FIFO emptying will be delayed until the FIFO fill level is exceeded. 10. Start the processing of FIFO data. Use the PBS[2:0] packet byte status bits to decide what is to be done with the FIFO data. a) If PBS[2:0] = 001, discard data byte read in step 5 and set the LINK ACTIVE software flag. b) If PBS[2:0] = 010, discard the data byte read in step 5 and clear the LINK ACTIVE software flag. c) If PBS[2:0] = 1XX, store the last byte of the packet, decrement the PACKET COUNT, and check the PBS[1:0] bits for CRC or NVB errors before deciding whether or not to keep the packet. d) If PBS[2:0] = 000, store the packet data. 11. If FE = 0 and INTR = 1 or FE = 0 and EMPTY FIFO = 1, go to step 5 else clear the EMPTY FIFO software flag and leave this interrupt service routine to wait for the next interrupt. The link state is typically a local software variable. The link state is inactive if the RDLC is receiving all ones or receiving bit-oriented codes which contain a sequence of eight ones. The link state is active if the RDLC is receiving flags or data. If the RDLC data transfer is operating in the polled mode, processor operation is exactly as shown above for the interrupt driven mode, except that the entry to the service routine is from a timer, rather than an interrupt.
14.4 T1 Automatic Performance Report Format
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Table 84
- Performance Report Message Structure and Contents
Octet No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Notes:
Bit 8
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 FLAG SAPI TEI CONTROL C/R
Bit 1 EA EA
G3 FE G3 FE G3 FE G3 FE
LV SE LV SE LV SE LV SE
G4 LB G4 LB G4 LB G4 LB
U1 G1 U1 G1 U1 G1 U1 G1 FCS FCS
U2 R U2 R U2 R U2 R
G5 G2 G5 G2 G5 G2 G5 G2
SL Nm SL Nm SL Nm SL Nm
G6 NI G6 NI G6 NI G6 NI
FLAG
1. The order of transmission of the bits is LSB (Bit 1) to MSB (Bit 8).
Table 85 Octet No. - Performance Report Message Structure Notes Octet Contents Interpretation
1 2 3 4 5,6 7,8
01111110 00111000 00111010 00000001 00000011 Variable Variable
Opening LAPD Flag From CI: TEI=0,EA=1 Unacknowledged Frame Data for latest second (T') Data for Previous Second(T'-1) SAPI=14, C/R=0, EA=0 From carrier: SAPI=14,C/R=1,EA=0
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Octet No.
Octet Contents
Interpretation
9,10 11,12 13,14 15
Table 86 Bit Value
Variable Variable Variable 01111110
Data for earlier Second(T'-2) Data for earlier Second(T'-3) CRC16 Frame Check Sequence Closing LAPD flag
- Performance Report Message Contents Interpretation
G1=1 G2=1 G3=1 G4=1 G5=1 G6=1 SE=1 FE=1 LV=1 SL=1 LB=1 U1,U2=0 R=0 NmNI=00,01,10, 11
14.5
CRC ERROR EVENT =1 1Using the Transmit Line Pulse Generator
The internal D/A pulse waveform template registers, accessible via the microprocessor bus, can be used to create a custom waveform. These 120 pulse waveform storage registers are accessed indirectly through XLPG Pulse Waveform Storage Write Address and XLPG Pulse Waveform Storage Data register. The values written into the pulse waveform storage registers correspond to one of 127 quantized levels. 24 samples are output during every transmit clock cycle.
PROPRIETARY AND CONFIDENTIAL
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The waveform being programmed is completely arbitrary and programming must be done properly in order to meet the various T1 and E1 template specifications. The SCALE[4:0] bits of Line Driver Configuration Register bits are used to obtain a proper output amplitude. It must also be noted that since samples from the 5 UI are added before driving the DAC, it is possible to create arithmetic overflows. The XLPG detects overflows and saturates the resulting value to -62 or +62 as appropriate. However, it is recommended that the pulse amplitude be programmed such that overflows are avoided. It is possible to verify if an overflow condition occurred by reading the OVRFLV register bit after programming a new waveform and transmission of data. The following tables contain the waveform values to be programmed for different situations. Table 87 to Table 96 specify waveform values typically used for T1 long haul and short haul transmission. Table 97 to Table 103 specify waveform values for compliance to the AT&T TR62411 ACCUNET T1.5 pulse template. This is particularly useful where compliance to the jitter specification of TR62411 is desired. Table 104 and Table 105 specify waveform values for E1 transmission.
Table 87 - Transmit Waveform Values for T1 Long Haul (LBO 0 dB): UI #0 UI #1 UI #2 UI #3 UI #4
Sample number
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
00 0A 20 32 3E 3D 3C 3B 3A 39 39 38 37 36 34
44 44 43 43 42 42 41 41 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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Sample number
UI #0
UI #1
UI #2
UI #3
UI #4
16 17 18 19 20 21 22 23 24
29 4F 4C 4A 49 47 47 46 46
00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00
Note: SCALE[4:0] programmed to 0CH.
Table 88 - Transmit Waveform Values for T1 Long Haul (LBO 7.5 dB): UI #0 UI #1 UI #2 UI #3 UI #4
Sample number
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
00 01 02 04 08 0C 10 16 1A 1E 22 26 2A 2B 2C 2D
10 0E 0C 0A 08 06 04 02 01 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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Sample number
UI #0
UI #1
UI #2
UI #3
UI #4
17 18 19 20 21 22 23 24
2C 28 24 20 1C 18 14 12
00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00
Note: SCALE[4:0] programmed to 07H.
Table 89 - Transmit Waveform Values for T1 Long Haul (LBO 15 dB): UI #0 UI #1 UI #2 UI #3 UI #4
Sample number
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
00 00 00 00 01 02 04 07 0A 0D 10 14 18 1B 1E 21 24
2A 28 26 24 22 20 1E 1C 1B 19 18 16 15 13 12 10 0F
09 08 08 07 07 06 06 05 05 05 04 04 04 03 03 03 03
01 01 01 01 01 01 01 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
PROPRIETARY AND CONFIDENTIAL
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Sample number
UI #0
UI #1
UI #2
UI #3
UI #4
18 19 20 21 22 23 24
27 2A 2D 30 30 2E 2C
0D 0D 0B 0B 0A 0A 09
03 02 02 02 02 02 02
00 00 00 00 00 00 00
00 00 00 00 00 00 00
Note: SCALE[4:0] programmed to 03H.
Table 90 - Transmit Waveform Values for T1 Long Haul (LBO 22.5 dB): UI #0 UI #1 UI #2 UI #3 UI #4
Sample number
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
00 00 00 00 00 00 01 01 01 02 03 05 07 09 0B 0E 10 13
1F 20 21 22 22 23 23 24 23 23 22 22 21 20 1E 1D 1B 1B
16 15 15 14 13 12 12 11 10 10 0F 0E 0E 0D 0C 0C 0B 0A
06 05 05 05 04 04 04 03 03 03 03 03 02 02 02 02 02 02
01 01 01 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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Sample number
UI #0
UI #1
UI #2
UI #3
UI #4
19 20 21 22 23 24
15 17 19 1B 1D 1E
1A 19 19 18 17 17
0A 09 08 08 07 06
02 01 01 01 01 01
00 00 00 00 00 00
Note: SCALE[4:0] programmed to 02H.
Table 91 - Transmit Waveform Values for T1 Short Haul (0 - 110 ft.): UI #0 UI #1 UI #2 UI #3 UI #4
Sample number
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
00 0A 20 3F 3F 3F 3C 3B 3A 39 39 38 37 36 34 29 59 55 50
45 44 43 43 42 42 41 41 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
PROPRIETARY AND CONFIDENTIAL
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Sample number
UI #0
UI #1
UI #2
UI #3
UI #4
20 21 22 23 24
4D 4A 48 46 46
00 00 00 00 00
00 00 00 00 00
00 00 00 00 00
00 00 00 00 00
Note: SCALE[4:0] programmed to 0CH.
Table 92 - Transmit Waveform Values for T1 Short Haul (110 - 220 ft.): UI #0 UI #1 UI #2 UI #3 UI #4
Sample number
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
00 0A 3F 3F 36 34 30 2F 2E 2D 2C 2B 2A 28 26 4A 68 54 4F 4A
44 44 43 43 42 42 41 41 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
PROPRIETARY AND CONFIDENTIAL
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Sample number
UI #0
UI #1
UI #2
UI #3
UI #4
21 22 23 24
49 47 47 46
00 00 00 00
00 00 00 00
00 00 00 00
00 00 00 00
Note: SCALE[4:0] programmed to 10H.
Table 93 - Transmit Waveform Values for T1 Short Haul (220 - 330 ft.): UI #0 UI #1 UI #2 UI #3 UI #4
Sample number
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
00 0A 3F 3A 3A 38 30 2F 2E 2D 2C 2B 2A 29 23 4A 6C 60 4F 4A 49
44 44 43 43 42 42 41 41 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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Sample number
UI #0
UI #1
UI #2
UI #3
UI #4
22 23 24
47 47 46
00 00 00
00 00 00
00 00 00
00 00 00
Note: SCALE[4:0] programmed to 11H.
Table 94 - Transmit Waveform Values for T1 Short Haul (330 - 440 ft.): UI #0 UI #1 UI #2 UI #3 UI #4
Sample number
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22
00 0A 3F 3F 3F 3F 2F 2E 2D 2C 2B 2A 29 28 19 4A 7F 60 4F 4A 49 47
44 44 43 43 42 42 41 41 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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Sample number
UI #0
UI #1
UI #2
UI #3
UI #4
23 24
47 46
00 00
00 00
00 00
00 00
Note: SCALE[4:0] programmed to 12H.
Table 95 - Transmit Waveform Values for T1 Short Haul (440 - 550 ft.): UI #0 UI #1 UI #2 UI #3 UI #4
Sample number
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
00 0A 3F 3F 3F 3F 30 2B 2A 29 28 27 26 26 24 4A 7F 7F 4F 4A 49 47 47
44 44 43 43 42 42 41 41 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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Sample number
UI #0
UI #1
UI #2
UI #3
UI #4
24
46
00
00
00
00
Note: SCALE[4:0] programmed to 14H.
Table 96 - Transmit Waveform Values for T1 Short Haul (550 - 660 ft.): UI #0 UI #1 UI #2 UI #3 UI #4
Sample number
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
00 0A 3F 3F 3F 3F 3F 30 2A 29 28 27 26 25 24 4A 7F 7F 5F 50 49 47 47 46
44 44 43 43 42 42 41 41 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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Note: SCALE[4:0] programmed to 15H.
Table 97 0 dB): - TR62411 Transmit Waveform Values for T1 Long Haul (LBO UI #0 UI #1 UI #2 UI #3 UI #4
Sample number
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
00 0A 20 32 3E 3D 3C 3B 3A 39 39 38 37 36 34 29 4F 4C 4A 46 44 42 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
Note: SCALE[4:0] programmed to 0CH.
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Table 98 110 ft.):
- TR62411 Transmit Waveform Values for T1 Short Haul (0 UI #0 UI #1 UI #2 UI #3 UI #4
Sample number
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
00 0A 20 3F 3F 3F 3C 3B 3A 39 39 38 37 36 34 29 4C 4A 48 46 44 42 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
Note: SCALE[4:0] programmed to 0CH.
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Table 99 220 ft.):
- TR62411 Transmit Waveform Values for T1 Short Haul (110 - UI #0 UI #1 UI #2 UI #3 UI #4
Sample number
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
00 0A 3F 3F 36 34 30 2F 2E 2D 2C 2B 2A 28 26 4A 68 4A 48 46 44 42 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
Note: SCALE[4:0] programmed to 10H.
PROPRIETARY AND CONFIDENTIAL
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Table 100 330 ft.):
- TR62411 Transmit Waveform Values for T1 Short Haul (220 - UI #0 UI #1 UI #2 UI #3 UI #4
Sample number
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
00 0A 3F 3A 3A 38 30 2F 2E 2D 2C 2B 2A 29 23 4A 6C 4A 48 46 44 42 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
Note: SCALE[4:0] programmed to 11H.
PROPRIETARY AND CONFIDENTIAL
395
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Table 101 440 ft.):
- TR62411 Transmit Waveform Values for T1 Short Haul (330 - UI #0 UI #1 UI #2 UI #3 UI #4
Sample number
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
00 0A 3F 3F 3F 3F 2F 2E 2D 2C 2B 2A 29 28 19 4A 7F 54 48 46 44 42 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
Note: SCALE[4:0] programmed to 12H.
PROPRIETARY AND CONFIDENTIAL
396
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Table 102 550 ft.):
- TR62411 Transmit Waveform Values for T1 Short Haul (440 - UI #0 UI #1 UI #2 UI #3 UI #4
Sample number
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
00 0A 3F 3F 3F 3F 30 2B 2A 29 28 27 26 26 24 4A 7F 7F 4A 46 44 42 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
Note: SCALE[4:0] programmed to 14H.
PROPRIETARY AND CONFIDENTIAL
397
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Table 103 660 ft.):
- TR62411 Transmit Waveform Values for T1 Short Haul (550 - UI #0 UI #1 UI #2 UI #3 UI #4
Sample number
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
00 0A 3F 3F 3F 3F 3F 30 2A 29 28 27 26 25 24 4A 7F 7F 5F 50 49 44 42 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
Note: SCALE[4:0] programmed to 15H.
PROPRIETARY AND CONFIDENTIAL
398
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Table 104
- Transmit Waveform Values for E1 120 Ohm: UI #0 UI #1 UI #2 UI #3 UI #4
Sample number
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
00 00 0A 3F 3F 39 38 36 36 35 35 35 35 35 35 2D 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
Note: SCALE[4:0] programmed to 0CH.
PROPRIETARY AND CONFIDENTIAL
399
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Table 105
- Transmit Waveform Values for E1 75 Ohm: UI #0 UI #1 UI #2 UI #3 UI #4
Sample number
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
00 00 0A 3E 3E 3E 3C 3C 3A 3A 3A 3A 3A 3A 3A 35 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
Note: SCALE[4:0] programmed to 0BH.
PROPRIETARY AND CONFIDENTIAL
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14.6
Using the Line Receiver
The line receiver must be properly initialized for correct operation. Several register bits must be programmed, and a RAM table must be initialized. Note that two registers must be programmed to non-default values. The Reserved bit of the RLPS Equalizer Configuration register must be set to logic 1. The EQ_VREF[5:0] bits of the RLPS Equalizer Voltage Reference register must be programmed to 2CH (`b101100) for T1 mode or 34H (`b110100) for E1 mode. Since the line receiver supports both E1 and T1 standards over either short haul or long haul cables, the line receiver has two normal modes of operation, as selected by the T1/E1B bit of the Global Configuration register. Table 107 and Table 108 contain the values to be programmed into the equalizer RAM for T1 and E1 mode, respectively. The RLPS equalizer RAM content is programmed by the RLPS Equalization Indirect Data registers (0D8H to 0DBH) for each address location. The address location is given by the quadrant's RLPS Equalization Indirect Address register (0FCH). A read or write request is done by setting the RWB bit in the quadrant's RLPS Equalization Read/WriteB Select register (0FDH). Table 106 below summarizes the values the RLPS registers are to contain.
Table 106 - RLPS Register Programming Data Value Binary Hex Register Address Register Name
XX000XX1 X000X000 00000001 00000001 00000000 1XXXXXXX 00000000
01H 00H 01H 01H 00H 80H 00H
0F8H 0F9H 0FAH 0FBH 0FCH 0FDH 0FEH
RLPS Configuration and Status RLPS ALOS Detection/ Clearance Threshold RLPS ALOS Detection Period RLPS ALOS Clearance Time RLPS Equalization Indirect Address RLPS Equalization RAM Read/WriteB Select RLPS Equalizer Loop Status and Control
PROPRIETARY AND CONFIDENTIAL
401
STANDARD PRODUCT DATA SHEET PMC-1970624 ISSUE 10
PM4351 COMET
COMBINED E1/T1 TRANSCEIVER
00001011 * * * * XX101100 XX110100
0BH * * * * 2CH 34H
0FFH 0D8H 0D9H 0DAH 0DBH 0DCH
RLPS Equalizer Configuration RLPS Equalization Indirect Data[31:24] RLPS Equalization Indirect Data[23:16] RLPS Equalization Indirect Data[15:8] RLPS Equalization Indirect Data[7:0] RLPS Equalizer Voltage Reference (T1 mode) (E1 mode)
Access to the Equalizer RAM is provided by means of Registers FCH, FDH, D8H, D9H, FAH, and FBH. A typical programming sequence follows. This programming sequence is repeated for each of the 256 Equalizer RAM Addresses.
WRITE D8H WRITE D9H WRITE DAH WRITE DBH ACTION FDH action> WRITE FCH PAUSE <31 - 24 Bits of Data> <23 - 16 Bits of Data> <15 - 8 Bits of Data> <7 - 0 Bits of Data>

Table 107
- RLPS Equalizer RAM Table (T1 mode) Content (MSB..LSB) RAM Address Content (MSB..LSB)
RAM Address
00D 01D
03 FE 18 40H 03 F6 18 40H
128D 129D
97 5E 7A C0H 97 5E 7A C0H
PROPRIETARY AND CONFIDENTIAL
402
STANDARD PRODUCT DATA SHEET PMC-1970624 ISSUE 10
PM4351 COMET
COMBINED E1/T1 TRANSCEIVER
RAM Address
Content (MSB..LSB)
RAM Address
Content (MSB..LSB)
02D 03D 04D 05D 06D 07D 08D 09D 10D 11D 12D 13D 14D 15D 16D 17D 18D 19D 20D 21D 22D 23D 24D 25D 26D 27D 28D 29D 30D 31D 32D
03 EE 18 40H 03 E6 18 40H 03 DE 18 40h 03 D6 18 40H 03 D6 18 40H 03 D6 18 40H 03 CE 18 40H 03 CE 18 40H 03 CE 18 40H 03 CE 18 40H 03 C6 18 40H 03 C6 18 40H 03 C6 18 40H 0B BE 18 40H 0B BE 18 40H 0B BE 18 40H 0B BE 18 40H 0B B6 18 40H 0B B6 18 40H 0B B6 18 40H 0B B6 18 40H 13 AE 18 38H 13 AE 18 3CH 13 AE 18 40H 13 AE 18 40H 13 AE 18 40H 13 AE 18 40H 1B B6 18 B8H 1B AE 18 B8H 1B AE 18 BCH 1B AE 18 C0H
130D 131D 132D 133D 134D 135D 136D 137D 138D 139D 140D 141D 142D 143D 144D 145D 146D 147D 148D 149D 150D 151D 152D 153D 154D 155D 156D 157D 158D 159D 160D
97 5E 7A C0H 9F 5E 8A C0H 9F 5E 8A C0H 9F 5E 8A C0H 9F 5E 8A C0H 9F 5E 8A C0H A7 56 9A C0H A7 56 9A C0H A7 56 9A C0H A7 56 9A C0H A7 56 AA C0H A7 56 AA C0H A7 56 AA C0H AF 4E AA C0H AF 4E AA C0H AF 4E AA C0H AF 4E AA C0H AF 4E AA C0H B7 46 AA C0H B7 46 AA C0H B7 46 AA C0H B7 46 AA C0H B7 46 AA C0H B7 46 AA C0H B7 46 AA C0H B7 46 BA C0H B7 46 BA C0H B7 46 BA C0H BF 4E BB 40H BF 4E BB 40H BF 4E BB 40H
PROPRIETARY AND CONFIDENTIAL
403
STANDARD PRODUCT DATA SHEET PMC-1970624 ISSUE 10
PM4351 COMET
COMBINED E1/T1 TRANSCEIVER
RAM Address
Content (MSB..LSB)
RAM Address
Content (MSB..LSB)
33D 34D 35D 36D 37D 38D 39D 40D 41D 42D 43D 44D 45D 46D 47D 48D 49D 50D 51D 52D 53D 54D 55D 56D 57D 58D 59D 60D 61D 62D 63D
1B AE 18 C0H 23 A6 18 C0H 23 A6 18 C0H 23 A6 18 C0H 23 A6 18 C0H 23 A6 18 C0H 23 9E 18 C0H 23 9E 18 C0H 23 9E 18 C0H 23 9E 18 C0H 23 9E 18 C0H 2B 96 18 C0H 2B 96 18 C0H 2B 96 18 C0H 33 96 19 40H 37 96 19 40H 37 96 19 40H 37 96 19 40H 3F 9E 19 C0H 3F 9E 19 C0H 3F 9E 19 C0H 3F A6 1A 40H 3F A6 1A 40H 3F A6 1A 40H 3F A6 1A 40H 3F 96 19 C0H 3F 96 19 C0H 3F 96 19 C0H 3F 96 19 C0H 47 9E 1A 40H 47 9E 1A 40H
161D 162D 163D 164D 165D 166D 167D 168D 169D 170D 171D 172D 173D 174D 175D 176D 177D 178D 179D 180D 181D 182D 183D 184D 185D 186D 187D 188D 189D 190D 191D
BF 4E BB 40H BF 4E BB 40H BF 4E BB 40H BF 4E BB 40H BF 4E BB 40H BF 4E BB 40H BE 46 CB 40H BE 46 CB 40H BE 46 CB 40H BE 46 CB 40H BE 46 CB 40H BE 46 CB 40H BE 46 DB 40H BE 46 DB 40H BE 46 DB 40H C6 3E CB 40H C6 3E CB 40H C6 3E DB 40H C6 3E DB 40H C6 3E DB 40H C6 44 DB 40H C6 44 DB 40H C6 44 DB 40H C6 44 DB 40H C6 3C DB 40H C6 3C DB 40H C6 3C DB 40H C6 3C DB 40H D6 34 DB 40H D6 34 DB 40H D6 34 DB 40H
PROPRIETARY AND CONFIDENTIAL
404
STANDARD PRODUCT DATA SHEET PMC-1970624 ISSUE 10
PM4351 COMET
COMBINED E1/T1 TRANSCEIVER
RAM Address
Content (MSB..LSB)
RAM Address
Content (MSB..LSB)
64D 65D 66D 67D 68D 69D 70D 71D 72D 73D 74D 75D 76D 77D 78D 79D 80D 81D 82D 83D 84D 85D 86D 87D 88D 89D 90D 91D 92D 93D 94D
47 9E 1A 40H 47 96 1A 40H 47 96 1A 40H 47 96 1A 40H 47 96 1A 40H 4F 8E 1A 40H 4F 8E 1A 40H 4F 8E 1A 40H 4F 8E 1A 40H 4F 8E 1A 40H 57 86 1A 40H 57 86 1A 40H 57 86 1A 40H 57 86 1A 40H 57 86 1A 40H 5F 86 1A C0H 5F 86 1A C0H 5F 86 1A C0H 5F 86 1A C0H 5F 86 1A C0H 5F 86 1A C0H 5F 7E 1A C0H 5F 7E 1A C0H 5F 7E 1A C0H 5F 7E 1A C0H 5F 7E 1A C0H 67 7E 2A C0H 67 7E 2A C0H 67 7E 2A C0H 67 7E 2A C0H 67 76 2A C0H
192D 193D 194D 195D 196D 197D 198D 199D 200D 201D 202D 203D 204D 205D 206D 207D 208D 209D 210D 211D 212D 213D 214D 215D 216D 217D 218D 219D 220D 221D 222D
D6 34 DB 40H D6 34 DB 40H DE 2C DB 3CH DE 2C DB 3CH DE 2C DB 3CH E6 2C DB 40H E6 2C DB 40H E6 2C DB 40H E6 2C DB 40H E6 2C DB 40H E6 2C EB 40H E6 2C EB 40H E6 2C EB 40H EE 2C FB 40H EE 2C FB 40H EE 2C FB 40H EE 2D 0B 40H EE 2D 0B 40H EE 2D 0B 40H EE 2D 0B 40H EE 2D 0B 40H F5 25 0B 38H F5 25 0B 3CH F5 25 0B 40H F5 25 1B 40H F5 25 1B 40H F5 25 1B 40H F5 25 1B 40H F5 25 1B 40H FD 25 2B 40H FD 25 2B 40H
PROPRIETARY AND CONFIDENTIAL
405
STANDARD PRODUCT DATA SHEET PMC-1970624 ISSUE 10
PM4351 COMET
COMBINED E1/T1 TRANSCEIVER
RAM Address
Content (MSB..LSB)
RAM Address
Content (MSB..LSB)
95D 96D 97D 98D 99D 100D 101D 102D 103D 104D 105D 106D 107D 108D 109D 110D 111D 112D 113D 114D 115D 116D 117D 118D 119D 120D 121D 122D 123D 124D 125D
67 76 2A C0H 67 76 2A C0H 67 76 2A C0H 67 76 2A C0H 6F 6E 2A C0H 6F 6E 2A C0H 6F 6E 2A C0H 6F 6E 2A C0H 77 6E 3A C0H 77 6E 3A C0H 77 6E 3A C0H 77 6E 3A C0H 7F 66 3A C0H 7F 66 3A C0H 7F 66 4A C0H 7F 66 4A C0H 7F 66 4A C0H 7F 66 4A C0H 87 66 5A C0H 87 66 5A C0H 87 66 5A C0H 87 66 5A C0H 87 66 5A C0H 87 5E 5A C0H 87 5E 5A C0H 87 5E 5A C0H 87 5E 5A C0H 87 5E 5A C0H 8F 5E 6A C0H 8F 5E 6A C0H 8F 5E 6A C0H
223D 224D 225D 226D 227D 228D 229D 230D 231D 232D 233D 234D 235D 236D 237D 238D 239D 240D 241D 242D 243D 244D 245D 246D 247D 248D 249D 250D 251D 252D 253D
FD 25 2B 40H FD 25 2B 40H FD 25 27 40H FD 25 27 40H FD 25 27 40H FD 25 23 40H FD 25 23 40H FD 25 23 40H FD 25 33 40H FD 25 33 40H FD 25 33 40H FD 25 33 40H FD 25 33 40H FD 25 33 40H FC 25 33 40H FC 25 33 40H FC 25 43 40H FC 25 43 40H FC 25 43 40H FC 25 43 44H FC 25 43 48H FC 25 43 4CH FC 25 43 BCH FC 25 43 C0H FC 25 43 C0H FC 23 43 C0H FC 23 43 C0H FC 23 43 C0H FC 21 43 C0H FC 21 43 C0H FC 21 53 C0H
PROPRIETARY AND CONFIDENTIAL
406
STANDARD PRODUCT DATA SHEET PMC-1970624 ISSUE 10
PM4351 COMET
COMBINED E1/T1 TRANSCEIVER
RAM Address
Content (MSB..LSB)
RAM Address
Content (MSB..LSB)
126D 127D
Table 108
8F 5E 6A C0H 97 5E 7A C0H
254D 255D
FC 21 53 C0H FC 21 53 C0H
- RLPS Equalizer RAM Table (E1 mode) Content (MSB..LSB) RAM Address Content (MSB..LSB)
RAM Address
00D 01D 02D 03D 04D 05D 06D 07D 08D 09D 10D 11D 12D 13D 14D 15D 16D 17D 18D 19D 20D 21D 22D 23D 24D 25D
07 DE 18 2CH 07 DE 18 2CH 07 D6 18 2CH 07 D6 18 2CH 07 D6 18 2CH 07 CE 18 2CH 07 CE 18 2CH 07 CE 18 2CH 07 C6 18 2CH 07 C6 18 2CH 07 C6 18 2CH 07 BE 18 2CH 07 BE 18 2CH 07 BE 18 2CH 07 BE 18 2CH 07 BE 18 2CH 07 B6 18 2CH 07 B6 18 2CH 07 B6 18 2CH 07 B6 18 2CH 07 B6 18 2CH 07 AE 18 2CH 07 AE 18 2CH 07 AE 18 2CH 07 AE 18 2CH 07 AE 18 2CH
128D 129D 130D 131D 132D 133D 134D 135D 136D 137D 138D 139D 140D 141D 142D 143D 144D 145D 146D 147D 148D 149D 150D 151D 152D 153D
97 4E AF 2CH 97 4E AF 2CH 97 4E AB 2CH 97 4E AB 2CH 97 4E AB 2CH 9F 4E AB 2CH 9F 4E BB 2CH 9F 4E BB 2CH 9F 4E BB 2CH 9F 4E CB 2CH A7 4E CB 2CH A7 4E CB 2CH A7 46 CB 2CH A7 46 CB 2CH A7 46 CB 2CH A7 46 DB 2CH AF 46 DB 2CH AF 46 EB 2CH AF 46 EB 2CH AF 4E EB 2CH AE 4E EB 2CH AE 4E EB 2CH B5 46 FB 2CH B5 54 FB 2CH B5 4C FB 2CH B5 54 FB 2CH
PROPRIETARY AND CONFIDENTIAL
407
STANDARD PRODUCT DATA SHEET PMC-1970624 ISSUE 10
PM4351 COMET
COMBINED E1/T1 TRANSCEIVER
RAM Address
Content (MSB..LSB)
RAM Address
Content (MSB..LSB)
26D 27D 28D 29D 30D 31D 32D 33D 34D 35D 36D 37D 38D 39D 40D 41D 42D 43D 44D 45D 46D 47D 48D 49D 50D 51D 52D 53D 54D 55D 56D
07 B6 18 ACH 07 AE 18 ACH 07 AE 18 ACH 07 AE 18 ACH 07 AE 18 ACH 07 A6 18 ACH 07 A6 18 ACH 07 A6 18 ACH 07 A6 18 ACH 07 9E 18 ACH 07 A6 19 2CH 07 A6 19 2CH 07 A6 19 2CH 0F A6 19 2CH 0F A6 19 2CH 0F 9E 19 2CH 0F 9E 19 2CH 0F 9E 19 2CH 17 9E 19 2CH 17 A6 19 ACH 17 9E 19 ACH 17 9E 19 ACH 17 96 19 ACH 1F 96 19 ACH 1F 96 19 ACH 1F 8E 19 ACH 1F 8E 19 ACH 1F 8E 19 ACH 27 8E 19 ACH 27 8E 1A 2CH 27 8E 1A 2CH
154D 155D 156D 157D 158D 159D 160D 161D 162D 163D 164D 165D 166D 167D 168D 169D 170D 171D 172D 173D 174D 175D 176D 177D 178D 179D 180D 181D 182D 183D 184D
B5 54 FB 2CH BD 54 FB 2CH BD 4C FB 2CH BD 4C FB 2CH BD 4C FB 2CH BD 44 EB 2CH C5 44 FB 2CH C5 44 FB 2CH C5 44 FB 2CH C5 45 0B 2CH C5 45 0B 2CH C5 45 0B 2CH CD 45 0B 2CH CD 45 0B 2CH CD 3D 0B 2CH CD 3D 0B 2CH CD 3D 0B 2CH D5 3D 0B 2CH D5 3D 0B 2CH D5 3D 1B 2CH D5 3D 1B 2CH D5 3D 1B 2CH DD 3D 1B 2CH DD 3D 1B 2CH DD 35 1B 2CH DD 35 1B 2CH DD 35 1B 2CH E5 35 1B 2CH E5 35 1B 2CH E5 2D 1B 2CH E5 2D 1B 2CH
PROPRIETARY AND CONFIDENTIAL
408
STANDARD PRODUCT DATA SHEET PMC-1970624 ISSUE 10
PM4351 COMET
COMBINED E1/T1 TRANSCEIVER
RAM Address
Content (MSB..LSB)
RAM Address
Content (MSB..LSB)
57D 58D 59D 60D 61D 62D 63D 64D 65D 66D 67D 68D 69D 70D 71D 72D 73D 74D 75D 76D 77D 78D 79D 80D 81D 82D 83D 84D 85D 86D 87D
27 8E 1A 2CH 27 8E 1A 2CH 2F 86 1A 2CH 2F 86 1A 2CH 2F 86 1A 2CH 2F 7E 1A 2CH 2F 7E 1A 2CH 2F 7E 1A 2CH 37 7E 1A 2CH 37 7E 1A ACH 37 7E 1A ACH 37 7E 1A ACH 37 7E 1A ACH 3F 7E 2A ACH 3F 7E 2A ACH 3F 76 2A ACH 3F 86 2B 2CH 3F 7E 2B 2CH 47 7E 2B 2CH 47 7E 2F 2CH 47 7E 2F 2CH 47 7E 2F 2CH 47 76 2F 2CH 4F 76 2F 2CH 4F 76 2F 2CH 4F 6E 2F 2CH 4F 6E 2F 2CH 4F 6E 2F 2CH 57 6E 2F 2CH 57 6E 2F 2CH 57 6E 3F 2CH
185D 186D 187D 188D 189D 190D 191D 192D 193D 194D 195D 196D 197D 198D 199D 200D 201D 202D 203D 204D 205D 206D 207D 208D 209D 210D 211D 212D 213D 214D 215D
E5 2D 3B 2CH ED 2D 4B 2CH ED 2D 1B A8H ED 2D 1B ACH ED 2D 17 ACH ED 2D 17 ACH ED 2D 27 ACH F5 2D 27 ACH F5 2D 27 ACH F5 2D 2B ACH F5 2D 2B ACH F5 2D 2B ACH FD 2D 2B ACH FD 2B 2B ACH FD 2B 2B ACH FD 2B 2B ACH FD 2B 2B ACH FD 23 2B ACH FD 23 2B ACH FD 23 2B ACH FD 21 2B ACH FD 21 2B ACH FD 29 2B ACH FD 29 2B ACH FD 29 27 ACH FD 29 37 ACH FD 29 23 ACH FD 29 23 ACH FD 29 23 ACH FD 29 23 ACH FD 21 23 ACH
PROPRIETARY AND CONFIDENTIAL
409
STANDARD PRODUCT DATA SHEET PMC-1970624 ISSUE 10
PM4351 COMET
COMBINED E1/T1 TRANSCEIVER
RAM Address
Content (MSB..LSB)
RAM Address
Content (MSB..LSB)
88D 89D 90D 91D 92D 93D 94D 95D 96D 97D 98D 99D 100D 101D 102D 103D 104D 105D 106D 107D 108D 109D 110D 111D 112D 113D 114D 115D 116D 117D 118D
57 6E 3F 2CH 57 6E 3F 2CH 5F 6E 3F 2CH 5F 6E 4F 2CH 5F 6E 4F 2CH 5F 6E 4F 2CH 5F 66 4F 2CH 67 66 4F 2CH 67 66 4F 2CH 67 5E 4F 2CH 67 5E 4F 2CH 67 66 4F 2CH 67 66 4F 2CH 67 66 5F 2CH 6F 6E 5F 2CH 6F 6E 6F 2CH 6F 6E 6F 2CH 6F 6E 7F 2CH 6F 6E 7F 2CH 6F 6E 7F 2CH 77 66 7F 2CH 77 66 7F 2CH 77 5E 6F 2CH 77 5E 7F 2CH 77 5E 7F 2CH 7F 5E 7F 2CH 7F 5E 8F 2CH 7F 5E 8F 2CH 7F 5E 8F 2CH 87 56 8F 2CH 87 56 8F 2CH
216D 217D 218D 219D 220D 221D 222D 223D 224D 225D 226D 227D 228D 229D 230D 231D 232D 233D 234D 235D 236D 237D 238D 239D 240D 241D 242D 243D 244D 245D 246D
FD 21 23 ACH FD 21 23 ACH FD 21 33 ACH FD 21 33 ACH FD 21 33 ACH FD 21 43 ACH FD 21 43 ACH FD 21 43 ACH FC 21 43 ACH FC 21 43 ACH FC 19 43 ACH FC 19 43 ACH FC 19 43 ACH FC 19 43 ACH FC 19 53 ACH FC 19 53 ACH FC 19 53 ACH FC 19 53 ACH FC 19 63 ACH FC 19 63 ACH FC 19 63 ACH FC 19 73 ACH FC 19 73 ACH FC 19 73 ACH FC 19 73 ACH FC 19 73 ACH FC 19 83 ACH FC 19 83 ACH FC 19 83 ACH FC 19 83 ACH FC 19 83 ACH
PROPRIETARY AND CONFIDENTIAL
410
STANDARD PRODUCT DATA SHEET PMC-1970624 ISSUE 10
PM4351 COMET
COMBINED E1/T1 TRANSCEIVER
RAM Address
Content (MSB..LSB)
RAM Address
Content (MSB..LSB)
119D 120D 121D 122D 123D 124D 125D 126D 127D
87 56 8F 2CH 87 4E 8F 2CH 87 4E 8F 2CH 87 4E 8F 2CH 8F 4E 9F 2CH 8F 4E 9F 2CH 8F 4E AF 2CH 8F 4E AF 2CH 8F 4E AF 2CH
247D 248D 249D 250D 251D 252D 253D 254D 255D
FC 19 93 ACH FC 19 93 ACH FC 19 93 ACH FC 19 A3 ACH FC 19 A3 ACH FC 19 B3 ACH FC 19 B3 ACH FC 19 B3 ACH FC 19 B3 ACH
The Analog Loss Of Signal feature is available for short haul and ISDN signal levels only. (Other LOS variants are always available via the CDRC Interrupt Status and Alternate Loss of Signal registers.) For short haul and ISDN signal levels, the receiver monitors if the received signal exceeds a predefined peak amplitude and the ALOSV bit is set when this condition is not meet. The change in ALOSV state sets the ALOSI bit and can be enabled to assert the INTB. The RLPS is able to squelch the data in response to an assertion of ALOS. Since this action is not mandatory, it is not enabled by default. However it can be desirable to do so in which case data squelching can be enabled by setting the SQUELCHE register bit to logic 1.
14.6.1 T1 Performance Monitor Mode
The PM4351 COMET can operate in T1 Performance Monitor mode by programming the Equalizer to operate receiving a signal with a 20 dB flat loss from nominal as shown.
PROPRIETARY AND CONFIDENTIAL
411
STANDARD PRODUCT DATA SHEET PMC-1970624 ISSUE 10
PM4351 COMET
COMBINED E1/T1 TRANSCEIVER
Monitor Jack
2.42:1 Rm
RXTIP Rt RXRING
Zo
Zo
10Zo Rm 1:2 RXTIP Mon Rtm RXRING Mon Rm = (10Zo - Zo)/2 = 450ohms(T1) Rt = 18.7Ohms Rtm = Zo*2^2 = 400Ohms(T1) Zo = 100ohms
Zo
The RLPS receiver values to program the equalizer for T1 Performance Monitor Mode are contained in the below table.
Table 109 - RLPS Equalizer Lookup Table for T1 Performance Monitor Mode
RAM Address Content (MSB..LSB) RAM Address Content (MSB..LSB) RAM Address Content (MSB..LSB) RAM Address Content (MSB..LSB)
00D 01D 02D 03D 04D 05D 06D 07D 08D 09D 10D 11D 12D 13D 14D
03 FE 18 40H 03 FE 18 40H 03 FE 18 40H 03 FE 18 40H 03 FE 18 40H 03 FE 18 40H 03 FE 18 40H 03 FE 18 40H 03 F6 18 40H 03 F6 18 40H 03 F6 18 40H 03 F6 18 40H 03 F6 18 40H 03 F6 18 40H 03 F6 18 40H
64D 65D 66D 67D 68D 69D 70D 71D 72D 73D 74D 75D 76D 77D 78D
03 BE 18 40H 03 BE 18 40H 03 BE 18 40H 03 BE 18 40H 03 BE 18 40H 03 BE 18 40H 03 BE 18 40H 03 BE 18 40H 03 B6 18 40H 03 B6 18 40H 03 B6 18 40H 03 B6 18 40H 03 B6 18 40H 03 B6 18 40H 03 B6 18 40H
128D 129D 130D 131D 132D 133D 134D 135D 136D 137D 138D 139D 140D 141D 142D
03 76 18 40H 03 76 18 40H 03 76 18 40H 03 76 18 40H 03 76 18 40H 03 76 18 40H 03 76 18 40H 03 76 18 40H 03 6E 18 40H 03 6E 18 40H 03 6E 18 40H 03 6E 18 40H 03 6E 18 40H 03 6E 18 40H 03 6E 18 40H
192D 193D 194D 195D 196D 197D 198D 199D 200D 201D 202D 203D 204D 205D 206D
03 36 18 40H 03 36 18 40H 03 36 18 40H 03 36 18 40H 03 36 18 40H 03 36 18 40H 03 36 18 40H 03 36 18 40H 03 2E 18 40H 03 2E 18 40H 03 2E 18 40H 03 2E 18 40H 03 2E 18 40H 03 2E 18 40H 03 2E 18 40H
PROPRIETARY AND CONFIDENTIAL
412
STANDARD PRODUCT DATA SHEET PMC-1970624 ISSUE 10
PM4351 COMET
COMBINED E1/T1 TRANSCEIVER
RAM Address
Content (MSB..LSB)
RAM Address
Content (MSB..LSB)
RAM Address
Content (MSB..LSB)
RAM Address
Content (MSB..LSB)
15D 16D 17D 18D 19D 20D 21D 22D 23D 24D 25D 26D 27D 28D 29D 30D 31D 32D 33D 34D 35D 36D 37D 38D 39D 40D 41D 42D 43D 44D 45D 46D
03 F6 18 40H 03 EE 18 40H 03 EE 18 40H 03 EE 18 40H 03 EE 18 40H 03 EE 18 40H 03 EE 18 40H 03 EE 18 40H 03 EE 18 40H 03 E6 18 40H 03 E6 18 40H 03 E6 18 40H 03 E6 18 40H 03 E6 18 40H 03 E6 18 40H 03 E6 18 40H 03 E6 18 40H 03 DE 18 40H 03 DE 18 40H 03 DE 18 40H 03 DE 18 40H 03 DE 18 40H 03 DE 18 40H 03 DE 18 40H 03 DE 18 40H 03 D6 18 40H 03 D6 18 40H 03 D6 18 40H 03 D6 18 40H 03 D6 18 40H 03 D6 18 40H 03 D6 18 40H
79D 80D 81D 82D 83D 84D 85D 86D 87D 88D 89D 90D 91D 92D 93D 94D 95D 96D 97D 98D 99D 100D 101D 102D 103D 104D 105D 106D 107D 108D 109D 110D
03 B6 18 40H 03 A6 18 40H 03 A6 18 40H 03 A6 18 40H 03 A6 18 40H 03 A6 18 40H 03 A6 18 40H 03 A6 18 40H 03 A6 18 40H 03 9E 18 40H 03 9E 18 40H 03 9E 18 40H 03 9E 18 40H 03 9E 18 40H 03 9E 18 40H 03 9E 18 40H 03 9E 18 40H 03 96 18 40H 03 96 18 40H 03 96 18 40H 03 96 18 40H 03 96 18 40H 03 96 18 40H 03 96 18 40H 03 96 18 40H 03 8E 18 40H 03 8E 18 40H 03 8E 18 40H 03 8E 18 40H 03 8E 18 40H 03 8E 18 40H 03 8E 18 40H
143D 144D 145D 146D 147D 148D 149D 150D 151D 152D 153D 154D 155D 156D 157D 158D 159D 160D 161D 162D 163D 164D 165D 166D 167D 168D 169D 170D 171D 172D 173D 174D
03 6E 18 40H 03 66 18 40H 03 66 18 40H 03 66 18 40H 03 66 18 40H 03 66 18 40H 03 66 18 40H 03 66 18 40H 03 66 18 40H 03 5E 18 40H 03 5E 18 40H 03 5E 18 40H 03 5E 18 40H 03 5E 18 40H 03 5E 18 40H 03 5E 18 40H 03 5E 18 40H 03 56 18 40H 03 56 18 40H 03 56 18 40H 03 56 18 40H 03 56 18 40H 03 56 18 40H 03 56 18 40H 03 56 18 40H 03 4E 18 40H 03 4E 18 40H 03 4E 18 40H 03 4E 18 40H 03 4E 18 40H 03 4E 18 40H 03 4E 18 40H
207D 208D 209D 210D 211D 212D 213D 214D 215D 216D 217D 218D 219D 220D 221D 222D 223D 224D 225D 226D 227D 228D 229D 230D 231D 232D 233D 234D 235D 236D 237D 238D
03 2E 18 40H 03 26 18 40H 03 26 18 40H 03 26 18 40H 03 26 18 40H 03 26 18 40H 03 26 18 40H 03 26 18 40H 03 26 18 40H 03 1E 18 40H 03 1E 18 40H 03 1E 18 40H 03 1E 18 40H 03 1E 18 40H 03 1E 18 40H 03 1E 18 40H 03 1E 18 40H 03 16 18 40H 03 16 18 40H 03 16 18 40H 03 16 18 40H 03 16 18 40H 03 16 18 40H 03 16 18 40H 03 16 18 40H 03 0E 18 40H 03 0E 18 40H 03 0E 18 40H 03 0E 18 40H 03 0E 18 40H 03 0E 18 40H 03 0E 18 40H
PROPRIETARY AND CONFIDENTIAL
413
STANDARD PRODUCT DATA SHEET PMC-1970624 ISSUE 10
PM4351 COMET
COMBINED E1/T1 TRANSCEIVER
RAM Address
Content (MSB..LSB)
RAM Address
Content (MSB..LSB)
RAM Address
Content (MSB..LSB)
RAM Address
Content (MSB..LSB)
47D 48D 49D 50D 51D 52D 53D 54D 55D 56D 57D 58D 59D 60D 61D 62D 63D
03 D6 18 40H 03 CE 18 40H 03 CE 18 40H 03 CE 18 40H 03 CE 18 40H 03 CE 18 40H 03 CE 18 40H 03 CE 18 40H 03 CE 18 40H 03 C6 18 40H 03 C6 18 40H 03 C6 18 40H 03 C6 18 40H 03 C6 18 40H 03 C6 18 40H 03 C6 18 40H 03 C6 18 40H
111D 112D 113D 114D 115D 116D 117D 118D 119D 120D 121D 122D 123D 124D 125D 126D 127D
03 8E 18 40H 03 86 18 40H 03 86 18 40H 03 86 18 40H 03 86 18 40H 03 86 18 40H 03 86 18 40H 03 86 18 40H 03 86 18 40H 03 7E 18 40H 03 7E 18 40H 03 7E 18 40H 03 7E 18 40H 03 7E 18 40H 03 7E 18 40H 03 7E 18 40H 03 7E 18 40H
175D 176D 177D 178D 179D 180D 181D 182D 183D 184D 185D 186D 187D 188D 189D 190D 191D
03 4E 18 40H 03 46 18 40H 03 46 18 40H 03 46 18 40H 03 46 18 40H 03 46 18 40H 03 46 18 40H 03 46 18 40H 03 46 18 40H 03 3E 18 40H 03 3E 18 40H 03 3E 18 40H 03 3E 18 40H 03 3E 18 40H 03 3E 18 40H 03 3E 18 40H 03 3E 18 40H
239D 240D 241D 242D 243D 244D 245D 246D 247D 248D 249D 250D 251D 252D 253D 254D 255D
03 0E 18 40H 03 0E 18 40H 03 06 18 40H 03 06 18 40H 03 06 18 40H 03 06 18 40H 03 06 18 40H 03 06 18 40H 03 06 18 40H 03 06 18 40H 03 06 18 40H 03 06 18 40H 03 06 18 40H 03 06 18 40H 03 06 18 40H 03 06 18 40H 03 06 18 40H
14.7
Using the Test Pattern Generator
The pattern generator can be configured to generate pseudo random patterns or repetitive patterns as shown in the figure below:
Figure 38 - Pattern Generator Structure
LENGTH PS TAP
1
2
3
32
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The pattern generator consists of a 32-bit shift register and a single XOR gate. The XOR gate output is fed into the first stage of the shift register. The XOR gate inputs are determined by values written to the length register (PL[4:0]) and the tap register (PT[4:0], when the PS bit is low). When PS is high, the pattern detector functions as a recirculating shift register, with length determined by PL[4:0].
14.7.1 Common Test Patterns
The PRGD can be configured to monitor the standardized pseudo random and repetitive patterns described in ITU-T O.151, O.152 and O.153. The register configurations required to generate these patterns and others are indicated in the two tables below:
Table 110 Pattern Type - Pseudo-Random Pattern Generation (PS bit = 0) PT PL PI#1 PI#2 PI#3 PI#4 TINV RINV
23 -1 24 -1 25-1 26 -1 27 -1 27 -1 (Fractional T1 LB Activate) 27 -1 (Fractional T1 LB Deactivate) 29 -1 (O.153) 210 -1 211 -1 (O.152, O.153)
00 00 01 04 00 03
02 03 04 05 06 06
FF FF FF FF FF FF
FF FF FF FF FF FF
FF FF FF FF FF FF
FF FF FF FF FF FF
0 0 0 0 0 0
0 0 0 0 0 0
03
06
FF
FF
FF
FF
1
1
04 02 08
08 09 0A
FF FF FF
FF FF FF
FF FF FF
FF FF FF
0 0 0
0 0 0
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Pattern Type
PT
PL
PI#1
PI#2
PI#3
PI#4
TINV
RINV
215 -1 (O.151) 217 -1 218 -1 220 -1 (O.153) 220 -1 (O.151 QRSS bit=1) 221 -1 222 -1 223 -1 (O.151) 225 -1 228 -1 229 -1 231 -1
Table 111
0D 02 06 02 10
0E 10 11 13 13
FF FF FF FF FF
FF FF FF FF FF
FF FF FF FF FF
FF FF FF FF FF
1 0 0 0 0
1 0 0 0 0
01 00 11 02 02 01 02
14 15 16 18 1B 1C 1E
FF FF FF FF FF FF FF
FF FF FF FF FF FF FF
FF FF FF FF FF FF FF
FF FF FF FF FF FF FF
0 0 1 0 0 0 0
0 0 1 0 0 0 0
- Repetitive Pattern Generation (PS bit = 1) PT PL PI#1 PI#2 PI#3 PI#4 TINV RINV
Pattern Type
All ones All zeros Alternating ones/zeros Double alternating ones/zeros 3 in 24 1 in 16 1 in 8
00 00 00 00 00 00 00
00 00 01 03 17 0F 07
FF FE FE FC 22 01 01
FF FF FF FF 00 00 FF
FF FF FF FF 20 FF FF
FF FF FF FF FF FF FF
0 0 0 0 0 0 0
0 0 0 0 0 0 0
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Pattern Type
PT
PL
PI#1
PI#2
PI#3
PI#4
TINV
RINV
1 in 4 Inband loopback activate Inband loopback deactivate
00 00 00
03 04 02
F1 F0 FC
FF FF FF
FF FF FF
FF FF FF
0 0 0
0 0 0
Notes for the Pseudo Random and Repetitive Pattern Generation Tables
1. The PS bit and the QRSS bit are contained in the PRGD Control register 2. PT = Tap Register 3. PL = Shift Register Length Register 4. PI#1 = PRGD Pattern Insertion #1 Register 5. PI#2 = PRGD Pattern Insertion #2 Register 6. PI#3 = PRGD Pattern Insertion #3 Register 7. PI#4 = PRGD Pattern Insertion #4 Register 8. The TINV bit and the RINV bit are contained in the PRGD Control register
14.8 Using the Loopback Modes
The COMET provides four loopback modes to aid in network and system diagnostics. The network loopbacks (Payload and Line) can be initiated at any time via the P interface, but are usually initiated once an inband loopback activate code is detected. The system Diagnostic Digital loopback can be initiated at any time by the system via the P interface to check the path of system data through the framer. The Per-DS0 loopback permits the payload to be looped-back on a per-DS0 basis to allow network testing without taking an entire link off-line.
14.8.1 Line Loopback
When LINE loopback (LINELB) is initiated by setting the LINELB bit in the Master Diagnostics Register (00AH) to logic 1, the COMET is configured to internally connect the recovered data to the transmit jitter attenuator, TJAT. In analog mode (RUNI is logic 0), the data sent to the TJAT is the recovered data
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from the output of the CDRC block. In digital mode (RUNI is logic 1), the data sent to the TJAT is a sampled version of the RDAT digital input. Note that when line loopback is enabled, the contents of the TJAT Reference Clock Divisor and Output Clock Divisor registers should be programmed to 2FH in T1 or FFH in E1 to correctly attenuate the jitter on the receive clock. Conceptually, the data flow through the COMET in this loopback mode is illustrated in Figure 39. In this figure, the dashed lines represent connections in digital mode (RUNI is logic 1).
Figure 39 - Line Loopback
TDAT TCLKO BTPCM BTSIG BTCLK Transmitter T1-XBAS / E1-TRAN
BTIF
TX ELST
TJAT
XLPG
TXTIP TXRING
Line Loopback
BRPCM BRSIG BRCLK
BRIF
RX ELST
Framer T1-FRMR / E1-FRMR
RJAT
CDRC
RLPS
RXTIP RXRING
RDAT RCLKI
14.8.2 Payload Loopback
When PAYLOAD loopback (PAYLB) is initiated by setting the PAYLB bit in the Master Diagnostics Register (00AH) to logic 1, the COMET is configured to internally connect the output of its RX-ELST to the PCM input of its transmitter block. The data read out of RX-ELST is timed to the transmitter clock, and the transmit frame alignment indication is used to synchronize the output frame alignment of RX-ELST. The transmit frame alignment is either arbitrary (when the TX-ELST is used) or is specified by the BTFP input (when the TX-ELST is bypassed). Conceptually, the data flow through the COMET in this loopback mode is illustrated in Figure 40. Note that because the transmit and receive streams are not superframe aligned, any robbed-bit signaling in the receive stream will not fall in the correct frame once looped back and that transmit robbed-bit signaling will overwrite the looped back data if signaling insertion is enabled.
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Figure 40
- Payload Loopback
TDAT TCLKO BTPCM BTSIG BTCLK Transmitter T1-XBAS / E1-TRAN
BTIF
TX ELST
TJAT
XLPG
TXTIP TXRING
Payload Loopback
BRPCM BRSIG BRCLK
BRIF
RX ELST
Framer T1-FRMR / E1-FRMR
RJAT
CDRC
RLPS
RXTIP RXRING
RDAT RCLKI
14.8.3 Diagnostic Digital Loopback
When Diagnostic Digital loopback (DDLB) mode is initiated by setting the DDLB bit in the Master Diagnostics Register (00AH) to logic 1, the COMET is configured to internally direct the output of the TJAT to the inputs of the receiver section. In analog mode (RUNI is logic 0), the dual-rail RZ outputs of the TJAT are directed to the dual-rail inputs of the CDRC. In digital mode (RUNI is logic 1), the single-rail NRZ outputs of the TJAT are directed to the inputs of the RJAT. When configured for diagnostic digital loopback, the TUNI and RUNI bits must be set to the same value. Conceptually, the data flow through the COMET in this loopback condition is illustrated in Figure 41. In this figure, the dashed lines represent connections in digital mode (RUNI is logic 1).
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Figure 41
- Diagnostic Digital Loopback
TDAT TCLKO BTPCM BTSIG BTCLK Transmitter T1-XBAS / E1-TRAN
BTIF
TX ELST
TJAT
XLPG
TXTIP TXRING
Diagnostic Loopback
BRPCM BRSIG BRCLK
BRIF
RX ELST
Framer T1-FRMR / E1-FRMR
RJAT
CDRC
RLPS
RXTIP RXRING
RDAT RCLKI
14.8.4 Per-Channel Loopback
The T1 or E1 payload may be looped back on a per-channel or per-timeslot basis through the use of the TPSC. If all channels are looped back, the result is very similar to Payload Loopback. In order for per-channel loopback to operated correctly, the receive elastic store, RX-ELST, must be bypassed by setting the RXELSTBYP bit to logic 1 and the backplane receive interface must be set to clock master by setting the CMODE bit in the BRIF Receive Backplane Configuration register to logic 0. The LOOP bit must be set to logic 1 in the TPSC Internal Registers for each channel/timeslot desired to be looped back, and the PCCE bit in the TPSC Configuration register must be set to logic 1. When all these parameters are configured, the incoming receive channels/timeslots selected will overwrite their corresponding outgoing transmit channels/timeslots; the remaining transmit channels will pass through intact. Note that because the transmit and receive streams are not superframe aligned, any robbed-bit signaling in the receive stream will not fall in the correct frame once looped back and that transmit robbed-bit signaling will overwrite the looped back channel data if signaling insertion is enabled.
PROPRIETARY AND CONFIDENTIAL
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14.9
Using the Per-Channel Serial Controllers
14.9.1 Initialization
Before the TPSC (RPSC) block can be used, a proper initialization of the internal registers must be performed to eliminate erroneous control data from being produced on the block outputs. The output control streams should be disabled by setting the PCCE bit in the TPSC (RPSC) Configuration Register to logic 0. Then, all 96 locations of the TPSC (RPSC) must be filled with valid data. Finally, the output streams can be enabled by setting the PCCE bit in the TPSC (RPSC) Configuration Register to logic 1.
14.9.2 Direct Access Mode
Direct access mode to the TPSC or RPSC is not used in the COMET. However, direct access mode is selected by default whenever the COMET is reset. The IND bit within the TPSC and RPSC Configuration Registers must be set to logic 1 after a reset is applied.
14.9.3 Indirect Access Mode
Indirect access mode is selected by setting the IND bit in the TPSC or RPSC Configuration Register to logic 1. When using the indirect access mode, the status of the BUSY indication bit should be polled to determine the status of the microprocessor access: when the BUSY bit is logic 1, the TPSC or RPSC is processing an access request; when the BUSY bit is logic 0, the TPSC or RPSC has completed the request. The indirect write programming sequence for the TPSC (RPSC) is as follows: 1. Check that the BUSY bit in the TPSC (RPSC) P Access Status Register is logic 0. 2. Write the channel data to the TPSC (RPSC) Channel Indirect Data Buffer register. 3. Write RWB=0 and the channel address to the TPSC (RPSC) Channel Indirect Address/Control Register. 4. Poll the BUSY bit until it goes to logic 0. The BUSY bit will go to logic 1 immediately after step 3 and remain at logic 1 until the request is complete. 5. If there is more data to be written, go back to step 1.
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The indirect read programming sequence for the TPSC (RPSC) is as follows: 1. Check that the BUSY bit in the TPSC (RPSC) P Access Status Register is logic 0. 2. Write RWB=1 and the channel address to the TPSC (RPSC) Channel Indirect Address/Control Register. 3. Poll the BUSY bit, waiting until it goes to a logic 0. The BUSY bit will go to logic 1 immediately after step 2 and remain at logic 1 until the request is complete. 4. Read the requested channel data from the TPSC (RPSC) Channel Indirect Data Buffer register. 5. If there is more data to be read, go back to step 1.
14.10 Isolating an Interrupt
When the INTB pin goes low, the following procedure may be used to isolate the interrupt source. 1. Read the Interrupt Source Registers (Registers 007H, 008H and 009H). The bit corresponding to any block with an outstanding interrupt will be set to logic 1 in these registers. 2. Read the register(s) containing the interrupt status bits of the interrupting block in order to determine the event causing the interrupt. A typical block interrupt has two related bits: an enable bit (EVENTE for instance) and an interrupt status bit (EVENTI for instance). EVENTI will go to logic 1 when the triggering event occurs, and goes low when the register containing it is read; the setting of EVENTE has no effect on the value of EVENTI. However, a chip interrupt will only be caused if EVENTE is logic 1 and EVENTI is logic 1. Thus, both the interrupt status bit(s) and their respective enables may need to be read in order to determine which event caused an interrupt. Specific interrupt setups may differ from this model, however.
14.11 Using the Performance Monitor Counter Values
All PMON event counters are of sufficient length so that the probability of counter saturation over a one second interval is very small (less than 0.001%). The odds of any one of the counters saturating during a one second sampling interval go up as the bit error rate (BER) increases. At some point, the probability of counter saturation reaches 50%. This point varies, depending upon the framing format and the type of event being counted. The BER at which the probability of
PROPRIETARY AND CONFIDENTIAL
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counter saturation reaches 50% is shown for various counters in Table 112 for E1 mode, and in Table 113 for T1 mode.
Table 112 - PMON Counter Saturation Limits (E1 mode) BER
Counter
LCV FER CRCE FEBE
Table 113
4.0 X 10-3 4.0 X 10-3 cannot saturate cannot saturate
- PMON Counter Saturation Limits (T1 mode) Format BER
Counter
LCV FER
all SF T1DM SLC(R)96 ESF
5.3 x 10-3 1.6 x 10-3 1.6 x 10-3 3.2 x 10-2 6.4 x 10-2 1.28 x 10-1 1.83 x 10-2 2.56 x 10-1 cannot saturate
CRCE
SF T1DM SLC(R)96 ESF
Below these 50% points, the relationship between the BER and the counter event count (averaged over many one second samples) is essentially linear. Above the 50% point, the relationship between BER and the average counter event count is highly non-linear due to the likelihood of counter saturation. The following figures show this relationship for various counters and framing formats. These graphs can be used to determine the BER, given the average event count. In general, if the BER is above 10-3, the average counter event count cannot be used to determine the BER without considering the statistical effect of occasional counter saturation.
PROPRIETARY AND CONFIDENTIAL
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The following figures illustrate the expected count values for a range of Bit Error Ratios in E1 mode.
Figure 42 - LCV Count vs. BER (E1 mode)
Bit Error Rate (x 10 )
5 4 3 2 1 0 0 2000
Average Count Over Many 1 Second Intervals
-3
4000
6000
8000
10000
Line Code Violation Count Per Second
Figure 43
9 Bit Error Rate (x 10 -3 ) 8 7 6 5 4 3 2 1 0
- FER Count vs. BER (E1 mode)
Average Count Over Many 1 Second Intervals
0
50
100
150
200
250
Framing Bit Error Count Per Second
Since the maximum number of CRC sub-multiframes that can occur in one second is 1000, the 10-bit FEBE and CRCE counters cannot saturate in one second. Despite this, there is not a linear relationship between BER and CRC-4 block errors due to the nature of the CRC-4 calculation. At BERs below 10-4, there tends to be no more than one bit error per sub-multiframe, so the number of CRC-4 errors is generally equal to the number of bit errors, which is directly related to the BER. However, at BERs above 10-4, each CRC-4 error is often
PROPRIETARY AND CONFIDENTIAL
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due to more than one bit error. Thus, the relationship between BER and CRCE count becomes non-linear above a 10-4 BER. This must be taken into account when using CRC-4 counts to determine the BER. Since FEBEs are indications of CRCEs at the far end, and are accumulated identically to CRCEs, the same explanation holds for the FEBE event counter. The bit error rate for E1 can be calculated from the one-second PMON CRCE count by the following equation:
ae 8 ae oo c log c 1- CRCE / c e 8000 c 8*256 c c e
Bit Error Rate = 1 - 10
Figure 44
- CRCE Count vs. BER (E1 mode)
1.00E-02 1.00E-03 Bit Error Rate 1.00E-04 1.00E-05 1.00E-06 1.00E-07 0 200 400 600 CRCE 800 1000 1200
The following figures illustrate the expected count values for a range of Bit Error Ratios in T1 mode.
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Figure 45
8 7
Bit Error Rate (x 10-3 )
- LCV Count vs. BER (T1 mode)
Average Count Over Many 1 Second Intervals
6 5 4 3 2 1 0 0 2000 4000 6000 8000 10000 Line Code Violation Count Per Second
Figure 46
9
Bit Error Rate (x 10 -2 )
- FER Count vs. BER (T1 ESF mode)
Average Count Over Many 1 Second Intervals
8 7 6 5 4 3 2 1 0 0
50
100
150
200
250
Framing Bit Error Count Per Second
Since the maximum number of ESF superframes that can occur in one second is 333, the 9-bit BEE counter cannot saturate in one second in ESF framing format. Despite this, there is not a linear relationship between BER and BEE count, due to the nature of the CRC-6 calculation. At BERs below 10-4, there tends to be no more than one bit error per superframe, so the number of CRC-6 errors is generally equal to the number of bit errors, which is directly related to the BER. However, at BERs above 10-4, each CRC-6 error is often due to more than one bit error. Thus, the relationship between BER and BEE count becomes nonlinear above a 10-4 BER. This must be taken into account when using ESF CRC-6 counts to determine the BER.
PROPRIETARY AND CONFIDENTIAL
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COMBINED E1/T1 TRANSCEIVER
The bit error rate for T1 ESF can be calculated from the one-second PMON CRCE count by the following equation:
ae 24 ae oo c log c 1- BEE / c e 8000 c 24*193 c c e
Bit Error Rate = 1 - 10 Figure 47
- CRCE Count vs. BER (T1 ESF mode)
1.00E-02 1.00E-03 Bit Error Rate 1.00E-04 1.00E-05 1.00E-06 1.00E-07 0 50 100 150 200 250 300 350 CRCE
For T1 SF format, the CRCE and FER counts are identical, but the FER counter is smaller and should be ignored.
Figure 48
20
Bit Error Rate (x 10-2 )
- CRCE Count vs. BER (T1 SF mode)
18 16 14 12 10 8 6 4 2 0 0 200 400
Average Count Over Many 1 Second Intervals
600
800
1000
1200
Bit Error Event Count Per Second
PROPRIETARY AND CONFIDENTIAL
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COMBINED E1/T1 TRANSCEIVER
14.12 JTAG Support
The COMET supports the IEEE Boundary Scan Specification as described in the IEEE 1149.1 standards. The Test Access Port (TAP) consists of the five standard pins, TRSTB, TCK, TMS, TDI and TDO used to control the TAP controller and the boundary scan registers. The TRSTB input is the active-low reset signal used to reset the TAP controller. TCK is the test clock used to sample data on input, TDI and to output data on output, TDO. The TMS input is used to direct the TAP controller through its states. The basic boundary scan architecture is shown in Figure 49.
Figure 49 - Boundary Scan Architecture
TDI
Boundary Scan Register Device Identification Register Bypass Register
Instruction Register and Decode
Mux DFF
TDO
TMS
Test Access Port Controller
Control Select Tri-state Enable
TRSTB TCK
The boundary scan architecture consists of a TAP controller, an instruction register with instruction decode, a bypass register, a device identification register
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COMBINED E1/T1 TRANSCEIVER
and a boundary scan register. The TAP controller interprets the TMS input and generates control signals to load the instruction and data registers. The instruction register with instruction decode block is used to select the test to be executed and/or the register to be accessed. The bypass register offers a singlebit delay from primary input TDI to primary output TDO. The device identification register contains the device identification code. The boundary scan register allows testing of board inter-connectivity. The boundary scan register consists of a shift register place in series with device inputs and outputs. Using the boundary scan register, all digital inputs can be sampled and shifted out on primary output TDO. In addition, patterns can be shifted in on primary input TDI and forced onto all digital outputs.
TAP Controller
The TAP controller is a synchronous finite state machine clocked by the rising edge of primary input, TCK. All state transitions are controlled using primary TMS. The finite state machine is shown in Figure 50.
PROPRIETARY AND CONFIDENTIAL
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COMBINED E1/T1 TRANSCEIVER
Figure 50
- TAP Controller Finite State Machine
TRSTB=0
Test-Logic-Reset 1 0 1 Run-Test-Idle 0 1 Capture-DR 0 Shift-DR 1 Exit1-DR 0 Pause-DR 1 0 Exit2-DR 1 Update-DR 1 0 0 0 Exit2-IR 1 Update-IR 1 0 0 1 Exit1-IR 0 Pause-IR 1 0 Select-DR-Scan 0 1 Capture-IR 0 Shift-IR 1 0 1 1 Select-IR-Scan 0 1
All transitions dependent on input TMS
Test-Logic-Reset
The test logic reset state is used to disable the TAP logic when the device is in normal mode operation. The state is entered asynchronously by asserting input, TRSTB. The state is entered synchronously regardless of the current TAP
PROPRIETARY AND CONFIDENTIAL
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controller state by forcing input, TMS high for 5 TCK clock cycles. While in this state, the instruction register is set to the IDCODE instruction.
Run-Test-Idle
The run test/idle state is used to execute tests.
Capture-DR
The capture data register state is used to load parallel data into the test data registers selected by the current instruction. If the selected register does not allow parallel loads or no loading is required by the current instruction, the test register maintains its value. Loading occurs on the rising edge of TCK.
Shift-DR
The shift data register state is used to shift the selected test data registers by one stage. Shifting is from MSB to LSB and occurs on the rising edge of TCK.
Update-DR
The update data register state is used to load a test register's parallel output latch. In general, the output latches are used to control the device. For example, for the EXTEST instruction, the boundary scan test register's parallel output latches are used to control the device's outputs. The parallel output latches are updated on the falling edge of TCK.
Capture-IR
The capture instruction register state is used to load the instruction register with a fixed instruction. The load occurs on the rising edge of TCK.
Shift-IR
The shift instruction register state is used to shift both the instruction register and the selected test data registers by one stage. Shifting is from MSB to LSB and occurs on the rising edge of TCK.
Update-IR
The update instruction register state is used to load a new instruction into the instruction register. The new instruction must be scanned in using the Shift-IR state. The load occurs on the falling edge of TCK.
PROPRIETARY AND CONFIDENTIAL
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The Pause-DR and Pause-IR states are provided to allow shifting through the test data and/or instruction registers to be momentarily paused.
Boundary Scan Instructions
The following is an description of the standard instructions. Each instruction selects an serial test data register path between input TDI and output TDO.
BYPASS
The bypass instruction shifts data from input TDI to output TDO with one TCK clock period delay. The instruction is used to bypass the device.
EXTEST
The external test instruction allows testing of the interconnection to other devices. When the current instruction is the EXTEST instruction, the boundary scan register is placed between TDI and TDO. Primary device inputs can be sampled by loading the boundary scan register using the Capture-DR state. The sampled values can then be viewed by shifting the boundary scan register using the Shift-DR state. Primary device outputs can be controlled by loading patterns shifted in through input TDI into the boundary scan register using the Update-DR state.
SAMPLE
The sample instruction samples all the device inputs and outputs. For this instruction, the boundary scan register is placed between TDI and TDO. Primary device inputs and outputs can be sampled by loading the boundary scan register using the Capture-DR state. The sampled values can then be viewed by shifting the boundary scan register using the Shift-DR state.
IDCODE
The identification instruction is used to connect the identification register between TDI and TDO. The device's identification code can then be shifted out using the Shift-DR state.
STCTEST
The single transport chain instruction is used to test out the TAP controller and the boundary scan register during production test. When this instruction is the current instruction, the boundary scan register is connected between TDI and
PROPRIETARY AND CONFIDENTIAL
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TDO. During the Capture-DR state, the device identification code is loaded into the boundary scan register. The code can then be shifted out TDO using the Shift-DR state.
Boundary Scan Register
The boundary scan register is made up of 59 boundary scan cells, divided into input observation (in_cell), output (out_cell), and bidirectional (io_cell) cells. These cells are detailed in the pages which follow. The first 32 cells (58 down to 27) form the ID code register, and carry the code 443510CD for revision E COMET devices and 543510CD for revision F COMET devices. The remaining cells also have values which may be captured during the idcode instruction and shifted out if desired; these are included in brackets for reference. The cells are arranged as follows:
Table 114
Pin/ Enable
- Boundary Scan Register
Register Bit Cell Type I.D Bit. Pin/ Enable Register Bit Cell Type I.D. Bit
HIZ3,4 XCLK TCLKI TCLKO TDAT TFP BTCLK BTCLK_OEB 1 BTPCM BTSIG BTFP BTFP_OEB 1 CSB RSTB RDB WRB INTB D0 D0_OEB 1 D1
58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39
OUT_CELL IN_CELL IN_CELL OUT_CELL OUT_CELL OUT_CELL IO_CELL OUT_CELL IN_CELL IN_CELL IO_CELL OUT_CELL IN_CELL IN_CELL IN_CELL IN_CELL OUT_CELL IO_CELL OUT_CELL IO_CELL
05 15 05 05 0 1 0 0 0 0 1 1 0 1 0 1 0 0 0 1
D6_OEB 1 D7 D7_OEB 1 A0 A1 A2 A3 A4 A5 A6 A7 A8 ALE BRFP BRFP_OEB 1 BRSIG BRSIG_OEB 2 BRPCM BRPCM_OEB 2 BRCLK
28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
OUT_CELL IO_CELL OUT_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IO_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL IO_CELL
0 1 (0) (0) (0) (0) (0) (0) (0) (0) (0) (0) (0) (0) (0) (0) (0) (0) (0) (0)
PROPRIETARY AND CONFIDENTIAL
433
STANDARD PRODUCT DATA SHEET PMC-1970624 ISSUE 10
PM4351 COMET
COMBINED E1/T1 TRANSCEIVER
Pin/ Enable
Register Bit
Cell Type
I.D Bit.
Pin/ Enable
Register Bit
Cell Type
I.D. Bit
D1_OEB 1 D2 D2_OEB 1 D3 D3_OEB 1 D4 D4_OEB 1 D5 D5_OEB 1 D6
38 37 36 35 34 33 32 31 30 29
OUT_CELL IO_CELL OUT_CELL IO_CELL OUT_CELL IO_CELL OUT_CELL IO_CELL OUT_CELL IO_CELL
0 0 0 0 1 1 0 0 1 1
BRCLK_OEB 1 RSYNC RLCKI RCLKI_OEB 1 RDAT RDAT_OEB 1 TRIMF NC
NC_OEB
8 7 6 5 4 3 2 1 0
OUT_CELL OUT_CELL IO_CELL OUT_CELL IO_CELL OUT_CELL IN_CELL IO_CELL OUT_CELL
(0) (0) (0) (0) (0) (0) (0) (0) (0)
Notes:
1. These OEB signals, when set low, will set the corresponding bidirectional signal to an output. 2. These OEB signals, when set high, will set the corresponding output to high impedance. 3. When set high, TCLKO, TDAT, TFP, and RSYNC will be set to high impedance. 4. HIZ is the first bit in the boundary scan chain. 5. Bits 59:56 represent the revision identification code. "0100" indicates revision E. "0101" indicates revision F.
PROPRIETARY AND CONFIDENTIAL
434
STANDARD PRODUCT DATA SHEET PMC-1970624 ISSUE 10
PM4351 COMET
COMBINED E1/T1 TRANSCEIVER
Figure 51
IDCODE
- Input Observation Cell (IN_CELL)
Scan Chain Out
Input Pad
G1 G2 SHIFT-DR
INPUT to internal logic
I.D. Code bit CLOCK-DR
12 1 2 MUX 12 12
Scan Chain In
D C
In this diagram and those that follow, CLOCK-DR is equal to TCK when the current controller state is SHIFT-DR or CAPTURE-DR, and unchanging otherwise. The multiplexer in the centre of the diagram selects one of four inputs, depending on the status of select lines G1 and G2. The ID Code bit is as listed in the table above.
PROPRIETARY AND CONFIDENTIAL
435
STANDARD PRODUCT DATA SHEET PMC-1970624 ISSUE 10
PM4351 COMET
COMBINED E1/T1 TRANSCEIVER
Figure 52
- Output Cell (OUT_CELL)
Scan Chain Out
EXTEST OUTPUT or Enable f rom syst em logic IDCODE SHIFT - DR
G1 1 G1 G2 1 1 1 1 2 2 MUX 2 2 1
OUTPUT or Enable
MUX
D C
D C
I.D. code bit CLOCK-DR UPDA TE- DR
Scan Chain In
Figure 53
- Bidirectional Cell (IO_CELL)
Scan Chain Out INPUT to internal logic
EXTEST OUTPUT from internal logic IDCODE SHIFT-DR INPUT from pin
G1 1 G1 G2 12 1 2 MUX 12 12 D C D C 1
MUX
OUTPUT to pin
I.D. code bit CLOCK-DR UPDATE-DR
Scan Chain In
PROPRIETARY AND CONFIDENTIAL
436
STANDARD PRODUCT DATA SHEET PMC-1970624 ISSUE 10
PM4351 COMET
COMBINED E1/T1 TRANSCEIVER
Figure 54
- Layout of Output Enable and Bidirectional Cells
Scan Chain Out OUTPUT ENABLE from internal logic (0 = drive) INPUT to internal logic OUTPUT from internal logic
OUT_CELL
IO_CELL
I/O PAD
Scan Chain In
PROPRIETARY AND CONFIDENTIAL
437
STANDARD PRODUCT DATA SHEET PMC-1970624 ISSUE 10
PM4351 COMET
COMBINED E1/T1 TRANSCEIVER
15
ABSOLUTE MAXIMUM RATINGS
Maximum ratings are the worst case limits that the device can withstand without sustaining permanent damage. They are not indicative of normal mode operation conditions.
Ambient Temperature under Bias Storage Temperature Voltage on VDD with Respect to GND Voltage on BIAS with respect to GND Voltage on Any Pin Static Discharge Voltage Latchup current on any pin Maximum DC current on any pin Maximum Lead Temperature Maximum Junction Temperature
-55C to +125C -65C to +150C -0.3V to 4.6V VDD - 0.3V to 5.5V -0.3V to BIAS + 0.3V 1000 V 100 mA 20 mA +230 C +150 C
PROPRIETARY AND CONFIDENTIAL
438
STANDARD PRODUCT DATA SHEET PMC-1970624 ISSUE 10
PM4351 COMET
COMBINED E1/T1 TRANSCEIVER
16
D.C. CHARACTERISTICS
TA = -40C to +85C, VDD = 3.3 V 5%, VDD VBIAS 5.5 V (Typical Conditions: TA = 25C, VDD = 3.3 V, VBIAS = 5 V)
Table 115 Symbol - D.C. Characteristics Parameter Min Typ Max Units Conditions
VDD BIAS IBIAS VIL
Power Supply 3.135 5 V Tolerant Bias Current into 5 V Bias Input Low Voltage (TTL Only) Input High Voltage (TTL Only) Output or Bidirectional Low Voltage (TTL Only) 0 VDD
3.3 5.0 6.0
3.465 5.5
Volts Volts A VBIAS = 5.5V Guaranteed Input LOW Voltage Guaranteed Input HIGH Voltage VDD = min, IOL = -6 mA for BTCLK and BRCLK, -2 mA for all other digital outputs. Note 3 VDD = min, IOH = 6 mA for BTCLK and BRCLK, 2 mA for all other digital outputs. Note 3 TTL Schmitt trigger
0.8
Volts
VIH
2.0
BIAS
Volts
VOL
0.25
0.4
Volts
VOH
Output or Bidirectional High Voltage (TTL Only)
2.4
Volts
VT+ VTVTH
Reset Input High Voltage Reset Input Low Voltage Reset Input Hysteresis Voltage
2.0 0.8 0.5
Volts Volts Volts
PROPRIETARY AND CONFIDENTIAL
439
STANDARD PRODUCT DATA SHEET PMC-1970624 ISSUE 10
PM4351 COMET
COMBINED E1/T1 TRANSCEIVER
Symbol
Parameter
Min
Typ
Max
Units
Conditions
IILPU IIHPU IIL IIH CIN
Input Low Current Input High Current Input Low Current Input High Current Input Capacitance Output Capacitance Bi-directional Capacitance Operating Current
10 -10 -10 -10
60 0 0 0 5
100 +10 +10 +10
A A A A pF
VIL = GND. Notes 1, 3 VIH = VDD. Notes 1, 3 VIL = GND. Notes 2, 3 VIH = VDD. Notes 2, 3 Excluding Package, Package Typically 2 pF Excluding Package, Package Typically 2 pF Excluding Package, Package Typically 2 pF VDD = 3.465 V, T1 mode, 1.544 MHz backplane, transmitting all ones, short haul 550 to 660 ft. Outputs Unloaded VDD = 3.465 V, 85 C case temperature, T1 mode, 1.544 MHz backplane, transmitting 50% ones density, short haul 0 ft. Outputs Unloaded
COUT
5
pF
CIO
5
pF
IDDOPMAX
250
mA
PDISS
Power Dissipation
416
mW
Notes on D.C. Characteristics:
1. Input pin or bi-directional pin with internal pull-up resistor.
PROPRIETARY AND CONFIDENTIAL
440
STANDARD PRODUCT DATA SHEET PMC-1970624 ISSUE 10
PM4351 COMET
COMBINED E1/T1 TRANSCEIVER
2. Input pin or bi-directional pin without internal pull-up resistor 3. Negative currents flow into the device (sinking), positive currents flow out of the device (sourcing).
PROPRIETARY AND CONFIDENTIAL
441
STANDARD PRODUCT DATA SHEET PMC-1970624 ISSUE 10
PM4351 COMET
COMBINED E1/T1 TRANSCEIVER
17 17.1
A.C. TIMING CHARACTERISTICS Microprocessor Interface Timing Characteristics
(TA = -40C to +85C, VDD = 3.3 V 5%)
Table 116 Symbol - Microprocessor Read Access (Figure 55) Parameter Min Max Units
tSAR tHAR tSALR tHALR tVL tSLR tHLR tPRD tZRD tZINTH
Address to Valid Read Set-up Time Address to Valid Read Hold Time Address to Latch Set-up Time Address to Latch Hold Time Valid Latch Pulse Width Latch to Read Set-up Latch to Read Hold Valid Read to Valid Data Propagation Delay Valid Read Negated to Output Tri-state Valid Read Negated to INTB high
10 5 10 10 20 0 5 80 20 50
ns ns ns ns ns ns ns ns ns ns
PROPRIETARY AND CONFIDENTIAL
442
STANDARD PRODUCT DATA SHEET PMC-1970624 ISSUE 10
PM4351 COMET
COMBINED E1/T1 TRANSCEIVER
Figure 55
- Microprocessor Read Access Timing
tSAR
A[8:0] tS ALR
Valid
Address
tHAR tHALR
tV L ALE tS LR (CSB+RDB)
tHLR
tZ INTH INTB
tPRD D[7:0]
tZ RD
Valid Data
Notes on Microprocessor Read Timing:
1. Output propagation delay time is the time in nanoseconds from the 1.4 Volt point of the reference signal to the 1.4 Volt point of the output. 2. Maximum output propagation delays are measured with a 50 pF load on the Microprocessor Interface data bus, (D[7:0]). 3. A valid read cycle is defined as a logical OR of the CSB and the RDB signals. 4. Microprocessor Interface timing applies to normal mode register accesses only.
PROPRIETARY AND CONFIDENTIAL
443
STANDARD PRODUCT DATA SHEET PMC-1970624 ISSUE 10
PM4351 COMET
COMBINED E1/T1 TRANSCEIVER
5. When a set-up time is specified between an input and a clock, the set-up time is the time in nanoseconds from the 1.4 Volt point of the input to the 1.4 Volt point of the clock. 6. When a hold time is specified between an input and a clock, the hold time is the time in nanoseconds from the 1.4 Volt point of the clock to the 1.4 Volt point of the input. 7. In non-multiplexed address/data bus architectures ALE can be held high; parameters tSALR, tHALR, tVL, and tSLR, tHLR are not applicable. 8. Parameter tHAR is not applicable when address latching is used.
Table 117 Symbol - Microprocessor Write Access (Figure 56) Parameter Min Max Units
tSAW tSDW tSALW tHALW tVL tSLW tHLW tHDW tHAW tVWR
Address to Valid Write Set-up Time Data to Valid Write Set-up Time Address to Latch Set-up Time Address to Latch Hold Time Valid Latch Pulse Width Latch to Write Set-up Latch to Write Hold Data to Valid Write Hold Time Address to Valid Write Hold Time Valid Write Pulse Width
10 20 10 10 20 0 5 5 5 40
ns ns ns ns ns ns ns ns ns ns
PROPRIETARY AND CONFIDENTIAL
444
STANDARD PRODUCT DATA SHEET PMC-1970624 ISSUE 10
PM4351 COMET
COMBINED E1/T1 TRANSCEIVER
Figure 56
- Microprocessor Write Access Timing
A[8:0] tSALW tVL ALE tSAW (CSB+WRB)
Valid Address
tH ALW tSLW tHLW
tVWR
tH AW
tS DW D[7:0]
tH DW
Valid Data
Notes on Microprocessor Interface Write Timing:
1. A valid write cycle is defined as a logical OR of the CSB and the WRB signals. 2. Microprocessor Interface timing applies to normal mode register accesses only. 3. In non-multiplexed address/data bus architectures, ALE can be held high, parameters tSALW , tHALW , tVL, and tSLW , tHLW are not applicable. 4. Parameters tHAW and tSAW are not applicable if address latching is used. 5. Output propagation delay time is the time in nanoseconds from the 1.4 Volt point of the reference signal to the 1.4 Volt point of the output. 6. When a set-up time is specified between an input and a clock, the set-up time is the time in nanoseconds from the 1.4 Volt point of the input to the 1.4 Volt point of the clock. 7. When a hold time is specified between an input and a clock, the hold time is the time in nanoseconds from the 1.4 Volt point of the clock to the 1.4 Volt point of the input.
PROPRIETARY AND CONFIDENTIAL
445
STANDARD PRODUCT DATA SHEET PMC-1970624 ISSUE 10
PM4351 COMET
COMBINED E1/T1 TRANSCEIVER
17.2
Transmit Backplane Interface (Figure 57, Figure 58)
(TA = -40C to +85C, VDD = 3.3 V 5%)
Table 118 Symbol - Transmit Backplane Interface Description
BTCLK Average Frequency3 (T1 mode, CMS=0, RATE[1:0]='b00) BTCLK Average Frequency3 (CMS=0, RATE[1:0]='b01) BTCLK Average Frequency3 (T1 mode, CMS=1, RATE[1:0]='b00) BTCLK Average Frequency3 (CMS=0, RATE[1:0]='b10) or (CMS=1, RATE[1:0]='b01) BTCLK Average Frequency3 (CMS=0, RATE[1:0]='b11) or (CMS=1, RATE[1:0]='b10) BTCLK Average Frequency3 (CMS=1, RATE[1:0]='b11) BTCLK Duty Cycle4 tSBTCLK tHBTCLK tPBTFP BTCLK to Backplane Input Set-up Time1 BTCLK to Backplane Input Hold Time2 BTCLK to BTFP Output Propagation Delay
Min
Typ - 200 ppm Typ - 200 ppm Typ - 200 ppm Typ - 200 ppm Typ - 200 ppm Typ - 200 ppm 35 20 20 -20
Typ
1.544
Max
Typ + 200 ppm Typ + 200 ppm Typ + 200 ppm Typ + 200 ppm Typ + 200 ppm Typ + 200 ppm 65
Units
MHz
2.048 3.088
MHz MHz
4.096
MHz
8.192
MHz
16.384
MHz % ns ns
50
ns
PROPRIETARY AND CONFIDENTIAL
446
STANDARD PRODUCT DATA SHEET PMC-1970624 ISSUE 10
PM4351 COMET
COMBINED E1/T1 TRANSCEIVER
Figure 57
- Backplane Transmit Input Timing Diagram
BTPCM, BTSIG, BTFP (input)
Valid tS BTC LK tH BTC LK
BTCLK Data Sam pled on Rising Edge BTPCM, BTSIG, BTFP (input)
Valid tS BTC LK tH BTC LK
BTCLK
Data Sam pled on Falling Edge
PROPRIETARY AND CONFIDENTIAL
447
STANDARD PRODUCT DATA SHEET PMC-1970624 ISSUE 10
PM4351 COMET
COMBINED E1/T1 TRANSCEIVER
Figure 58
- Backplane Transmit Output Timing Diagram
BTCLK
BTFP (output)
Valid
tPBTF P Fram e Pulse O utput on Rising Edge
BTCLK
BTFP (output)
Valid
tPBTF P Fram e Pulse Output on Falling Edge
17.3
Receive Backplane Interface (Figure 59, Figure 60)
(TA = -40C to +85C, VDD = 3.3 V 5%)
Table 119 Symbol - Receive Backplane Interface Description
BRCLK Average Frequency3 (T1 mode, CMS=0, RATE[1:0]='b00) BRCLK Average Frequency3 (CMS=0, RATE[1:0]='b01) BRCLK Average Frequency3 (T1 mode, CMS=1, RATE[1:0]='b00)
Min
Typ - 200 ppm Typ - 200 ppm Typ - 200 ppm
Typ
1.544
Max
Typ + 200 ppm Typ + 200 ppm Typ + 200 ppm
Units
MHz
2.048 3.088
MHz MHz
PROPRIETARY AND CONFIDENTIAL
448
STANDARD PRODUCT DATA SHEET PMC-1970624 ISSUE 10
PM4351 COMET
COMBINED E1/T1 TRANSCEIVER
Symbol
Description
BRCLK Average Frequency3 (CMS=0, RATE[1:0]='b10) or (CMS=1, RATE[1:0]='b01) BRCLK Average Frequency3 (CMS=0, RATE[1:0]='b11) or (CMS=1, RATE[1:0]='b10) BRCLK Average Frequency3 (CMS=1, RATE[1:0]='b11) BRCLK Duty Cycle4
Min
Typ - 200 ppm Typ - 200 ppm Typ - 200 ppm 35 20 20 -20 -20
Typ
4.096
Max
Typ + 200 ppm Typ + 200 ppm Typ + 200 ppm 65
Units
MHz
8.192
MHz
16.384
MHz % ns ns
tSBRFP tHBRFP tPBRCLK tZBRCLK
BRFP to BRCLK Input Set-up Time1 BRFP to BRCLK Input Hold Time2 BRCLK to Backplane Output Signals Propagation Delay7,8 BRCLK to Backplane Output Signals High Impedance
50 30
ns ns
PROPRIETARY AND CONFIDENTIAL
449
STANDARD PRODUCT DATA SHEET PMC-1970624 ISSUE 10
PM4351 COMET
COMBINED E1/T1 TRANSCEIVER
Figure 59
- Backplane Receive Input Timing Diagram
BRFP (input)
Valid tS BRFP tH BRFP
BRCLK
Fram e Pulse Sam pled on Rising Edge
BRFP (input)
Valid tS BRFP tH BRFP
BRCLK
Fram e Pulse Sam pled on Falling Edge
PROPRIETARY AND CONFIDENTIAL
450
STANDARD PRODUCT DATA SHEET PMC-1970624 ISSUE 10
PM4351 COMET
COMBINED E1/T1 TRANSCEIVER
Figure 60
- Backplane Receive Output Timing Diagram
BRCLK
BRPCM, BRSIG tPBRCLK
Valid
tZ BRCLK
Data O utput on Rising Edge
BRCLK
BRFP (output)
Valid
tPBRCLK FP Output on Rising Edge
PROPRIETARY AND CONFIDENTIAL
451
STANDARD PRODUCT DATA SHEET PMC-1970624 ISSUE 10
PM4351 COMET
COMBINED E1/T1 TRANSCEIVER
BRCLK
BRPCM, BRSIG tPBRCLK
Valid
tZ BRCLK
Data Output on Falling Edge
BRCLK
BRFP (output)
Valid
tPBRCLK FP O utput on Falling Edge
17.4
Receive Digital Interface (Figure 61)
(TA = -40C to +85C, VDD = 3.3 V 5%)
Table 120 Symbol - Receive Digital Interface Description Min Max Units
RCLKI Frequency (nominally 1.544 MHz 130 ppm or 2.048 MHz 50 ppm) RCLKI Duty Cycle4 tSRCLKI tHRCLKI RCLKI to RDAT Setup Time1 RCLKI to RDAT Hold Time2 30 20 20
2.1
MHz
70
% ns ns
PROPRIETARY AND CONFIDENTIAL
452
STANDARD PRODUCT DATA SHEET PMC-1970624 ISSUE 10
PM4351 COMET
COMBINED E1/T1 TRANSCEIVER
Figure 61
- Digital Receive Interface Timing Diagram
RDAT
Valid tS RCLKI tH RCLKI
RCLKI
W ith RFALL bit = 0
RDAT
Valid tS RCLKI tH RCLKI
RCLKI W ith RFALL bit = 1
17.5
Transmit Digital Interface (Figure 62)
(TA = -40C to +85C, VDD = 3.3 V 5%)
Table 121 Symbol - Transmit Digital Interface Description Min Max Units
tTCLKI
TCLKI Frequency, typically 1.544 MHz 130 ppm in T1 mode or 2.048 MHz 50 ppm in E1 mode TCLKI High Duration4 TCLKI Low Duration4 XCLK Frequency, typically 1.544 MHz 100 ppm in T1 mode or 2.048 MHz 100 ppm in E1 mode
1.543 2.047 160 160 1.543 2.047
1.545 2.049
MHz MHz ns ns
tHTCLKI tLTCLKI tXCLK
1.545 2.049
MHz MHz
PROPRIETARY AND CONFIDENTIAL
453
STANDARD PRODUCT DATA SHEET PMC-1970624 ISSUE 10
PM4351 COMET
COMBINED E1/T1 TRANSCEIVER
Symbol
Description
Min
Max
Units
tHXCLK tLXCLK tPTCLKO
Figure 62
XCLK High Duration4 XCLK Low Duration4 TCLKO to Digital Transmit Output Signals Propagation Delay
160 160 -20 50
ns ns ns
- Digital Transmit Interface Timing Diagram
tHTCLKI
tLTCLKI
tTCLKI
tH XCLK
tL XCLK
t XCLK
PROPRIETARY AND CONFIDENTIAL
454
STANDARD PRODUCT DATA SHEET PMC-1970624 ISSUE 10
PM4351 COMET
COMBINED E1/T1 TRANSCEIVER
TCLKO
TDAT, TFP
Valid
tP O TCLK W ith TRISE bit = 0
TCLKO
TDAT, TFP
Valid
tP O TCLK W ith TRISE bit = 1
17.6
JTAG Port Interface (Figure 63)
(TA = -40C to +85C, VDD = 3.3 V 5%)
Table 122 Symbol - JTAG Port Interface Description Min Max Units
TCK Frequency TCK Duty Cycle tSTMS tHTMS tSTDI tHTDI tPTDO tVTRSTB TMS Set-up time to TCK TMS Hold time to TCK TDI Set-up time to TCK TDI Hold time to TCK TCK Low to TDO Valid TRSTB Pulse Width 40 50 50 50 50 2 100
4 60
MHz % ns ns ns ns
50
ns ns
PROPRIETARY AND CONFIDENTIAL
455
STANDARD PRODUCT DATA SHEET PMC-1970624 ISSUE 10
PM4351 COMET
COMBINED E1/T1 TRANSCEIVER
Figure 63
- JTAG Port Interface Timing
TCK tS TMS TMS tS TDI TDI tH TDI tH TMS
TCK tP TDO TDO
tVTRSTB TRSTB
Notes on Input Timing:
1. When a set-up time is specified between an input and a clock, the set-up time is the time in nanoseconds from the 1.4 Volt point of the input to the 1.4 Volt point of the clock. 2. When a hold time is specified between an input and a clock, the hold time is the time in nanoseconds from the 1.4 Volt point of the clock to the 1.4 Volt point of the input.
PROPRIETARY AND CONFIDENTIAL
456
STANDARD PRODUCT DATA SHEET PMC-1970624 ISSUE 10
PM4351 COMET
COMBINED E1/T1 TRANSCEIVER
3. BTCLK and BRCLK instantaneous period variation of +/- 8% (typical) can be tolerated by the device, as long as the frequency specification of +/- 200ppm is complied with. 4. High pulse width is measured from the 1.4 Volt points of the rise and fall ramps. Low pulse width is measured from the 1.4 Volt points of the fall and rise ramps. 5. XCLK accuracy is 100 ppm. 6. TCLKI can be a jittered clock signal subject to the minimum high and low durations tHTCLKI, tLTCLKI. These durations correspond to nominal XCLK input frequencies.
Notes on Output Timing:
7. Output propagation delay time is the time in nanoseconds from the 1.4 Volt point of the reference signal to the 1.4 Volt point of the output. 8. Maximum output propagation delays are measured with a 50 pF load on the output.
PROPRIETARY AND CONFIDENTIAL
457
STANDARD PRODUCT DATA SHEET PMC-1970624 ISSUE 10
PM4351 COMET
COMBINED E1/T1 TRANSCEIVER
18
ORDERING AND THERMAL INFORMATION Table 123 Part No. - Ordering Information Description
PM4351-RI PM4351-NI
Table 124
80-Pin Metric Plastic Quad Flat Pack (MQFP) 81-Ball Chip Array Ball Grid Array (CABGA)
- Thermal Information
Forced Air (Linear Feet per Minute)
Part No.
Case Temperature
Theta J-A
1 2
Conv
100
200
300
400
500
PM4351-RI PM4351-NI
-40C to 85C -40C to 85C
Dense Board
62.1 43.2 99.5
4
54.8 40.7 92.9 45.8
49.1 39.2 87.8 44.4
45.0 38.5 84.0 43.5
42.4 38.2 81.0 43.0
41.1 38.0 78.5 42.7
JEDEC Board Dense Board
3
JEDEC Board
47.8
1. - Dense Board is defined as a 3S3P board and consists of a 3x3 array of PM4351-RI devices located as close to each other as board design rules allow. All PM4351-RI devices are assumed to be dissipating 0.416 Watts. Theta J-A listed is for the device in the middle of the array. 2. - JEDEC Board Theta J-A is the measured value for a single thermal device in the same package on a 2S2P board following EIA/JESD 51-3. 3. - Dense Board is defined as a 3S3P board and consists of a 3x3 array of PM4351-NI devices located as close to each other as board design rules allow. All PM4351-NI devices are assumed to be dissipating 0.416 Watts. Theta J-A listed is for the device in the middle of the array. 4. - JEDEC Board Theta J-A is the measured value for a single thermal device in the same package on a 2S2P board following EIA/JESD 51-3.
PROPRIETARY AND CONFIDENTIAL
458
STANDARD PRODUCT DATA SHEET PMC-1970624 ISSUE 10
PM4351 COMET
COMBINED E1/T1 TRANSCEIVER
19
MECHANICAL INFORMATION
PM4351-RI Package
D D1
80
A
1
Pin 1 Designator
e
E
E1
8-12 DEG
8-12 DEG
A2
SEE DETAIL A
0-10 DEG. STANDOFF
NOTES: 1) ALL DIMENSIONS IN MILLIMETER. 2) DIMENSIONS SHOWN ARE NOMINAL WITH TOLERANCES AS INDICATED. 3) FOOT LENGTH "L" IS MEASURED AT GAGE PLANE, 0.25 ABOVE SEATING PLANE.
A
.25
A1
SEATING PLANE C 0-7 DEG L b C
0.13-0.23
LEAD COPLANARITY ccc C
DETAIL A
PACKAGE TYPE: BODY SIZE: Dim. Min. Nom. Max. A 2.00 2.15 2.35 80 PIN METRIC PLASTIC QUAD FLATPACK-MQFP 14 x 14 x 2.0 MM A1 0.05 0.15 0.25 A2 1.95 2.00 2.10 D 16.95 17.20 17.45 D1 13.90 14.00 14.10 E 16.95 17.20 17.45 E1 13.90 14.00 14.10 L 0.73 0.88 1.03 0.65 0.38 0.10 e b 0.22 ccc
PROPRIETARY AND CONFIDENTIAL
459
STANDARD PRODUCT DATA SHEET PMC-1970624 ISSUE 10
PM4351 COMET
COMBINED E1/T1 TRANSCEIVER
PM4351-NI Package
A1 BA LL CO R NE R
0.20 -A-
9
-B-
8
7
6
D
54 D1
3
2
1
A1 BA LL CO R NE R
A A1 BA LL I.D. IN K MA RK B C D E E1E F G H J
e
A2
A
-Cb
0.10
SE AT IN G PLA N E
.15 A C A S B S .08 A C
A1
NO TE S: 1) ALL D IM EN SIO NS IN M ILLIM ET ER .
PROPRIETARY AND CONFIDENTIAL
460
STANDARD PRODUCT DATA SHEET PMC-1970624 ISSUE 10
PM4351 COMET
COMBINED E1/T1 TRANSCEIVER
CONTACTING PMC-SIERRA, INC.
PMC-Sierra, Inc. 105-8555 Baxter Place Burnaby, BC Canada V5A 4V7 Tel: Fax: (604) 415-6000 (604) 415-6200 document@pmc-sierra.com info@pmc-sierra.com apps@pmc-sierra.com http://www.pmc-sierra.com
Document Information: Corporate Information: Application Information: Web Site:
None of the information contained in this document constitutes an express or implied warranty by PMC-Sierra, Inc. as to the sufficiency, fitness or suitability for a particular purpose of any such information or the fitness, or suitability for a particular purpose, merchantability, performance, compatibility with other parts or systems, of any of the products of PMC-Sierra, Inc., or any portion thereof, referred to in this document. PMC-Sierra, Inc. expressly disclaims all representations and warranties of any kind regarding the contents or use of the information, including, but not limited to, express and implied warranties of accuracy, completeness, merchantability, fitness for a particular use, or non-infringement. In no event will PMC-Sierra, Inc. be liable for any direct, indirect, special, incidental or consequential damages, including, but not limited to, lost profits, lost business or lost data resulting from any use of or reliance upon the information, whether or not PMC-Sierra, Inc. has been advised of the possibility of such damage. (c) 2000 PMC-Sierra, Inc. PMC-1970624 (R10) ref PMC-1961273(R11) Issue date: Nov 2000
PMC-Sierra, Inc.
105 - 8555 Baxter Place Burnaby, BC Canada V5A 4V7 604 .415.6000

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